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path: root/llvm/lib/Target/RISCV
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* [RISCV] Support linker relax function call from auipc and jalr to jalShiva Chen2018-05-244-2/+17
* [RISCV] Lower the tail pseudoinstructionMandeep Singh Grang2018-05-236-17/+157
* [RISCV] Set CostPerUse for registersSameer AbuAsal2018-05-231-0/+11
* [RISCV] Add symbol diff relocation support for RISC-VAlex Bradbury2018-05-233-1/+38
* [RISCV] Correctly report sizes for builtin fixupsAlex Bradbury2018-05-231-15/+2
* MC: Separate creating a generic object writer from creating a target object w...Peter Collingbourne2018-05-213-14/+11
* MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an M...Peter Collingbourne2018-05-211-5/+6
* Support: Simplify endian stream interface. NFCI.Peter Collingbourne2018-05-181-4/+4
* [RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvancedShiva Chen2018-05-181-5/+22
* [RISCV] Separate base from offset in lowerGlobalAddressSameer AbuAsal2018-05-171-5/+10
* [RISCV] Implement MC layer support for the tail pseudoinstructionMandeep Singh Grang2018-05-173-3/+14
* [RISCV] Set isReMaterializable on ADDI and LUI instructionsAlex Bradbury2018-05-173-1/+11
* [RISCV] Add support for .half, .hword, .word, .dword directivesAlex Bradbury2018-05-172-0/+6
* [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxa...Shiva Chen2018-05-153-0/+14
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-143-20/+22
* [RISCV] Support .option rvc and norvc assembler directivesAlex Bradbury2018-05-116-2/+123
* Fix a bunch of places where operator-> was used directly on the return from d...Craig Topper2018-05-051-1/+1
* [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlotAlex Bradbury2018-04-262-0/+54
* [RISCV] Implement isZextFreeAlex Bradbury2018-04-262-0/+15
* [RISCV] Implement isTruncateFreeAlex Bradbury2018-04-262-0/+22
* [RISCV] Implement isLegalICmpImmediateAlex Bradbury2018-04-262-0/+5
* [RISCV] Implement isLegalAddImmediateAlex Bradbury2018-04-262-0/+5
* [RISCV] Implement isLegalAddressingMode for RISC-VAlex Bradbury2018-04-262-0/+30
* [RISCV] Allow call pseudoinstruction to be used to call a function name that ...Alex Bradbury2018-04-251-9/+12
* [RISCV] Expand function call to "call" pseudoinstructionShiva Chen2018-04-253-10/+18
* [RISCV] Support "call" pseudoinstruction in the MC layerShiva Chen2018-04-257-4/+110
* [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bitsAlex Bradbury2018-04-181-2/+3
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-189-266/+49
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-179-49/+266
* [RISCV] Fix assert message operatorMandeep Singh Grang2018-04-161-1/+1
* [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0Sameer AbuAsal2018-04-121-0/+2
* [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVCShiva Chen2018-04-121-2/+3
* [RISCV] Codegen support for RV32D floating point comparison operationsAlex Bradbury2018-04-123-11/+37
* [RISCV] Codegen support for RV32D floating point conversion operationsAlex Bradbury2018-04-122-0/+15
* [RISCV] Add codegen support for RV32D floating point arithmetic operationsAlex Bradbury2018-04-122-1/+33
* [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ...Alex Bradbury2018-04-126-22/+327
* [NFC] fix trivial typos in comments and error messageHiroshi Inoue2018-04-091-1/+1
* [RISCV] Tablegen-driven Instruction Compression.Sameer AbuAsal2018-04-068-5/+332
* Sort targetgen calls in lib/Target/*/CMakeLists.Nico Weber2018-04-041-5/+5
* [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to Code...Craig Topper2018-03-291-1/+1
* [RISCV] Use init_array instead of ctors for RISCV target, by defaultMandeep Singh Grang2018-03-244-1/+47
* Fix layering by moving ValueTypes.h from CodeGen to IRDavid Blaikie2018-03-231-1/+1
* [RISCV] Codegen support for RV32F floating point comparison operationsAlex Bradbury2018-03-214-17/+70
* [RISCV] Add codegen for RV32F floating point load/storeAlex Bradbury2018-03-205-12/+51
* [RISCV] Add codegen for RV32F arithmetic and conversion operationsAlex Bradbury2018-03-202-5/+104
* [RISCV] Preserve stack space for outgoing arguments when the function contain...Shiva Chen2018-03-202-18/+38
* [RISCV] Peephole optimisation for load/store of global values or constant add...Alex Bradbury2018-03-191-0/+95
* [RISCV] Implement MC relaxations for compressed instructions.Sameer AbuAsal2018-03-021-7/+80
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-0/+1
* [RISCV] Implement c.lui immediate operand constraintShiva Chen2018-02-223-10/+39
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