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path: root/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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* [Transforms][RISCV] Remove a "using namespace llvm" from an include file. Fix...Craig Topper2020-01-171-2/+2
* [RISCV] Enable the machine outliner for RISC-Vlewis-revill2019-12-191-0/+158
* Fix assertion failure in getMemOperandWithOffsetWidthKristof Beyls2019-12-171-1/+2
* [RISCV] Added isCompressibleInst() to estimate size in getInstSizeInBytes()Ana Pazos2019-12-161-1/+15
* [RISCV] Machine Operand Flag SerializationSam Elliott2019-12-091-0/+25
* Use MCRegister in copyPhysRegMatt Arsenault2019-11-111-2/+2
* [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hookLuís Marques2019-11-051-0/+55
* [RISCV] Add MachineInstr immediate verificationLuis Marques2019-10-161-2/+58
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-131-18/+38
* Revert "[RISCV] Support stack offset exceed 32-bit for RV64"Shiva Chen2019-09-131-37/+18
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-131-18/+37
* [RISCV] Convert registers from unsigned to RegisterLuis Marques2019-08-161-1/+1
* [risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-121-1/+1
* [RISCV] Don't acccess an invalidated iterator in RISCVInstrInfo::removeBranchAlex Bradbury2019-07-181-2/+2
* [RISCV] Add pseudo instruction for calls with explicit registerLewis Revill2019-06-261-0/+1
* [RISCV] Add lowering of global TLS addressesLewis Revill2019-06-191-0/+2
* [RISCV] Add lowering of addressing sequences for PICLewis Revill2019-06-111-0/+1
* [RISCV] Generate address sequences suitable for mcmodel=mediumAlex Bradbury2019-04-011-0/+1
* [RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()Alex Bradbury2019-03-111-2/+2
* Implementation of asm-goto support in LLVMCraig Topper2019-02-081-1/+2
* Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUIAna Pazos2019-01-251-0/+13
* Revert "[RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI"Ana Pazos2019-01-241-13/+0
* [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUIAna Pazos2019-01-241-0/+13
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [RISCV] Remove overzealous is64Bit checksAlex Bradbury2018-10-041-2/+1
* [RISCV] Add support for _interrupt attributeAna Pazos2018-07-261-2/+4
* [RISCV] Lower the tail pseudoinstructionMandeep Singh Grang2018-05-231-0/+1
* [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlotAlex Bradbury2018-04-261-0/+49
* [RISCV] Expand function call to "call" pseudoinstructionShiva Chen2018-04-251-0/+2
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-181-2/+11
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-171-11/+2
* [RISCV] Codegen support for RV32D floating point comparison operationsAlex Bradbury2018-04-121-7/+11
* [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ...Alex Bradbury2018-04-121-0/+4
* [RISCV] Codegen support for RV32F floating point comparison operationsAlex Bradbury2018-03-211-10/+31
* [RISCV] Implement support for the BranchRelaxation passAlex Bradbury2018-01-101-5/+110
* [RISCV] Implement branch analysisAlex Bradbury2018-01-101-0/+166
* [RISCV] Support stack frames and offsets up to 32-bitsAlex Bradbury2018-01-101-0/+20
* [RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/lo...Alex Bradbury2017-12-071-2/+2
* [RISCV] Initial support for function callsAlex Bradbury2017-11-081-1/+2
* [RISCV] Codegen for conditional branchesAlex Bradbury2017-11-081-0/+33
* [RISCV] Codegen support for memory operationsAlex Bradbury2017-11-081-0/+12
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+31
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