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| author | Lewis Revill <lewis.revill@embecosm.com> | 2019-06-26 10:35:58 +0000 |
|---|---|---|
| committer | Lewis Revill <lewis.revill@embecosm.com> | 2019-06-26 10:35:58 +0000 |
| commit | cf74881329d3b2bce063b70cbac85792a1b76b0f (patch) | |
| tree | 2b17416cf5c6ffd6c3e19152208560a2f4a0e52b /llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | |
| parent | e17a52ebeeb04fc2a860a80eec6e89683b0a7c42 (diff) | |
| download | bcm5719-llvm-cf74881329d3b2bce063b70cbac85792a1b76b0f.tar.gz bcm5719-llvm-cf74881329d3b2bce063b70cbac85792a1b76b0f.zip | |
[RISCV] Add pseudo instruction for calls with explicit register
This patch adds the PseudoCALLReg instruction which allows using an
explicit register operand as the destination for the return address.
GCC can successfully parse this form of the call instruction, which
would be used for calls to functions which do not use ra as the return
address register, such as the __riscv_save libcalls. This patch forms
the first part of an implementation of -msave-restore for RISC-V.
Differential Revision: https://reviews.llvm.org/D62685
llvm-svn: 364403
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 9d1361b4df7..2608906bb43 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -436,6 +436,7 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { case TargetOpcode::KILL: case TargetOpcode::DBG_VALUE: return 0; + case RISCV::PseudoCALLReg: case RISCV::PseudoCALL: case RISCV::PseudoTAIL: case RISCV::PseudoLLA: |
