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path: root/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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* [RISCV] Add DAGCombine for (SplitF64 (ConstantFP x))Alex Bradbury2019-03-301-0/+11
* [RISCV] Add basic RV32E definitions and MC layer supportAlex Bradbury2019-03-221-0/+3
* [RISCV] Optimize emission of SELECT sequencesAlex Bradbury2019-03-221-17/+90
* [RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()Alex Bradbury2019-03-111-2/+2
* [RISCV][NFC] Minor refactoring of CC_RISCVAlex Bradbury2019-03-091-7/+7
* [RISCV][NFC] Split out emitSelectPseudo from EmitInstrWithCustomInserterAlex Bradbury2019-03-091-16/+19
* [RISCV] Support -target-abi at the MC layer and for codegenAlex Bradbury2019-03-091-0/+6
* [RISCV][NFC] IsEligibleForTailCallOptimization -> isEligibleForTailCallOptimi...Alex Bradbury2019-02-211-6/+5
* [RISCV] Implement RV64D codegenAlex Bradbury2019-02-011-4/+7
* [RISCV] Add RV64F codegen supportAlex Bradbury2019-01-311-1/+74
* [RISCV] Add target DAG combine for bitcast fabs/fneg on RV32FDAlex Bradbury2019-01-251-3/+28
* [RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64MAlex Bradbury2019-01-251-30/+28
* [RISCV] Custom-legalise 32-bit variable shifts on RV64Alex Bradbury2019-01-251-32/+86
* Reapply "IR: Add fp operations to atomicrmw"Matt Arsenault2019-01-221-0/+6
* [RISCV] Quick fix for PR40333Alex Bradbury2019-01-221-1/+5
* Revert r351778: IR: Add fp operations to atomicrmwChandler Carruth2019-01-221-6/+0
* [RISCV] Fix build after r351778Alex Bradbury2019-01-221-3/+6
* IR: Add fp operations to atomicrmwMatt Arsenault2019-01-221-0/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [RISCV] Add codegen support for RV64AAlex Bradbury2019-01-171-32/+85
* [RISCV] Introduce codegen patterns for RV64M-only instructionsAlex Bradbury2019-01-121-5/+21
* [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructionsAlex Bradbury2019-01-121-0/+51
* [RISCV] Add support for the various RISC-V FMA instruction variantsAlex Bradbury2018-12-131-3/+1
* [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement fo...Alex Bradbury2018-11-301-0/+4
* [RISCV] Implement codegen for cmpxchg on RV32IAAlex Bradbury2018-11-291-0/+21
* [RISCV] Mark FREM as ExpandAlex Bradbury2018-11-151-1/+1
* [RISCV] Add some missing expansions for floating-point intrinsicsAlex Bradbury2018-11-021-0/+9
* [RISCV] Remove overzealous is64Bit checksAlex Bradbury2018-10-041-2/+2
* [RISCV] Bugfix for floats passed on the stack with the ILP32 ABI on RV32FAlex Bradbury2018-10-041-4/+7
* [RISCV][NFC] Fix naming of RISCVISelLowering::{LowerRETURNADDR,LowerFRAMEADDR}Alex Bradbury2018-10-041-5/+5
* [RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombineAlex Bradbury2018-10-031-0/+18
* [RISCV][NFC] Refactor LocVT<->ValVT converstion in RISCVISelLoweringAlex Bradbury2018-10-031-40/+33
* [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32AAlex Bradbury2018-09-191-2/+91
* [RISCV] Remove unused functionRoger Ferrer Ibanez2018-08-171-20/+0
* [RISCV] Add support for _interrupt attributeAna Pazos2018-07-261-0/+43
* [RISCV] Add codegen support for atomic load/stores with RV32AAlex Bradbury2018-06-131-2/+22
* [RISCV] Codegen support for atomic operations on RV32IAlex Bradbury2018-06-131-0/+3
* Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet2018-06-011-5/+0
* [RISCV] Lower the tail pseudoinstructionMandeep Singh Grang2018-05-231-8/+117
* [RISCV] Separate base from offset in lowerGlobalAddressSameer AbuAsal2018-05-171-5/+10
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-4/+4
* [RISCV] Implement isZextFreeAlex Bradbury2018-04-261-0/+14
* [RISCV] Implement isTruncateFreeAlex Bradbury2018-04-261-0/+20
* [RISCV] Implement isLegalICmpImmediateAlex Bradbury2018-04-261-0/+4
* [RISCV] Implement isLegalAddImmediateAlex Bradbury2018-04-261-0/+4
* [RISCV] Implement isLegalAddressingMode for RISC-VAlex Bradbury2018-04-261-0/+26
* [RISCV] Expand function call to "call" pseudoinstructionShiva Chen2018-04-251-4/+7
* [RISCV] Fix assert message operatorMandeep Singh Grang2018-04-161-1/+1
* [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVCShiva Chen2018-04-121-2/+3
* [RISCV] Codegen support for RV32D floating point comparison operationsAlex Bradbury2018-04-121-4/+12
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