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path: root/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Commit message (Expand)AuthorAgeFilesLines
* [SelectionDAG] Disallow indirect "i" constraintFangrui Song2019-12-291-1/+0
* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-131-1/+1
* [RISCV] Fix static analysis issuesLuis Marques2019-09-201-1/+1
* [RISCV] Lower inline asm constraint A for RISC-VLewis Revill2019-08-161-0/+3
* [RISCV] Support @llvm.readcyclecounter() IntrinsicSam Elliott2019-07-051-0/+7
* [RISCV][NFC] Add break to case statement in RISCVDAGToDAGISel::SelectAlex Bradbury2019-01-221-0/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [RISCV] Introduce codegen patterns for instructions introduced in RV64IAlex Bradbury2018-11-301-0/+34
* [RISCV] Constant materialisation for RV64IAlex Bradbury2018-11-161-1/+28
* [RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombineAlex Bradbury2018-10-031-12/+0
* [RISCV][NFCI] Handle redundant splitf64+buildpairf64 pairs during instruction...Alex Bradbury2018-10-031-39/+12
* [RISCV][NFC] Refactor RISCVDAGToDAGISel::SelectAlex Bradbury2018-10-031-12/+12
* [RISCV] Add machine function pass to merge base + offsetSameer AbuAsal2018-06-271-208/+0
* [RISCV] Add peepholes for Global Address lowering patternsSameer AbuAsal2018-05-291-0/+208
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-13/+14
* Fix a bunch of places where operator-> was used directly on the return from d...Craig Topper2018-05-051-1/+1
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-181-43/+22
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-171-22/+43
* [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ...Alex Bradbury2018-04-121-1/+41
* [RISCV] Peephole optimisation for load/store of global values or constant add...Alex Bradbury2018-03-191-0/+95
* [SelectionDAGISel] Add a debug print before call to Select. Adjust where blan...Craig Topper2018-01-261-3/+0
* [RISCV] Add basic support for inline asm constraintsAlex Bradbury2018-01-101-0/+19
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-111-0/+20
* [RISCV][NFC] Clean up RISCVDAGToDAGISel::SelectAlex Bradbury2017-11-211-14/+9
* [RISCV] Use register X0 (ZERO) for constant 0Alex Bradbury2017-11-211-0/+30
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+63
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