[RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombine

r343712 performed this optimisation during instruction selection. As Eli 
Friedman pointed out in post-commit review, implementing this as a DAGCombine 
might allow opportunities for further optimisations.

llvm-svn: 343741

1 files changed, 0 insertions, 12 deletions

diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index e61086bf0d3..e355b208a75 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -96,18 +96,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm));
     return;
   }
-  case RISCVISD::SplitF64: {
-    // If the input to SplitF64 is just BuildPairF64 then the operation is
-    // redundant. Instead, use BuildPairF64's operands directly. This pattern
-    // can't be written in tablegen due to the multiple outputs.
-    SDValue Op0 = Node->getOperand(0);
-    if (Op0->getOpcode() != RISCVISD::BuildPairF64)
-      break;
-    ReplaceUses(SDValue(Node, 0), Op0.getOperand(0));
-    ReplaceUses(SDValue(Node, 1), Op0.getOperand(1));
-    CurDAG->RemoveDeadNode(Node);
-    return;
-  }
   }
 
   // Select the default instruction.