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* [RISCV] Don't crash on unsupported relocationsLuís Marques2019-12-191-2/+11
| | | | | | | | | | Summary: Instead of crashing due to the `llvm_unreachable`, provide a proper error when invalid fixups/relocations are encountered. Reviewers: asb, lenary Reviewed By: asb Tags: #llvm Differential Revision: https://reviews.llvm.org/D71536
* [MC] Minor cleanup to MCFixup::Kind handling. NFC.Sam Clegg2019-08-231-1/+1
| | | | | | | | | | Prefer `MCFixupKind` where possible and add getTargetKind() to convert to `unsigned` when needed rather than scattering cast operators around the place. Differential Revision: https://reviews.llvm.org/D59890 llvm-svn: 369720
* [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for ↵Alex Bradbury2019-08-201-0/+5
| | | | | | | | | | | | | | | | | | the FDE location Follow binutils in using RISCV_32_PCREL for the FDE initial location. As explained in the relevant binutils commit <https://github.com/riscv/riscv-binutils-gdb/commit/a6cbf936e3dce68114d28cdf60d510a3f78a6d40>, the ADD/SUB pair of relocations is problematic in the presence of linker relaxation. This patch has the same end goal as D64715 but includes test changes and avoids adding a new global VariantKind to MCExpr.h (preferring RISCVMCExpr VKs like the rest of the RISC-V backend). Differential Revision: https://reviews.llvm.org/D66419 llvm-svn: 369375
* [llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere2019-08-151-1/+1
| | | | | | | | Now that we've moved to C++14, we no longer need the llvm::make_unique implementation from STLExtras.h. This patch is a mechanical replacement of (hopefully) all the llvm::make_unique instances across the monorepo. llvm-svn: 369013
* [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.Hsiangkai Wang2019-07-191-0/+4
| | | | | | | | | | | | | It is necessary to generate fixups in .debug_frame or .eh_frame as relaxation is enabled due to the address delta may be changed after relaxation. There is an opcode with 6-bits data in debug frame encoding. So, we also need 6-bits fixup types. Differential Revision: https://reviews.llvm.org/D58335 llvm-svn: 366524
* Revert "[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame."Hsiangkai Wang2019-07-181-4/+0
| | | | | | This reverts commit 17e3cbf5fe656483d9016d0ba9e1d0cd8629379e. llvm-svn: 366444
* [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.Hsiangkai Wang2019-07-181-0/+4
| | | | | | | | | | | | | It is necessary to generate fixups in .debug_frame or .eh_frame as relaxation is enabled due to the address delta may be changed after relaxation. There is an opcode with 6-bits data in debug frame encoding. So, we also need 6-bits fixup types. Differential Revision: https://reviews.llvm.org/D58335 llvm-svn: 366442
* [RISCV] Make RISCVELFObjectWriter::getRelocType check IsPCRelAlex Bradbury2019-07-161-25/+36
| | | | | | | | | | | Previously, this function didn't check the IsPCRel argument. But doing so is a useful check for errors, and also seemingly necessary for FK_Data_4 (which we produce a R_RISCV_32_PCREL relocation for if IsPCRel). Other than R_RISCV_32_PCREL, this should be NFC. Future exception handling related patches will include tests that capture this behaviour. llvm-svn: 366172
* [RISCV] Support assembling %tls_{ie,gd}_pcrel_hi modifiersLewis Revill2019-04-231-0/+4
| | | | | | | | | This patch adds support for parsing and assembling the %tls_ie_pcrel_hi and %tls_gd_pcrel_hi modifiers. Differential Revision: https://reviews.llvm.org/D55342 llvm-svn: 358994
* [RISCV] Support assembling TLS add and associated modifiersLewis Revill2019-04-041-0/+8
| | | | | | | | | | This patch adds support in the MC layer for parsing and assembling the 4-operand add instruction needed for TLS addressing. This also involves parsing the %tprel_hi, %tprel_lo and %tprel_add operand modifiers. Differential Revision: https://reviews.llvm.org/D55341 llvm-svn: 357698
* [RISCV] Support assembling @plt symbol operandsAlex Bradbury2019-04-021-0/+2
| | | | | | | | | | This patch allows symbols appended with @plt to parse and assemble with the R_RISCV_CALL_PLT relocation. Differential Revision: https://reviews.llvm.org/D55335 Patch by Lewis Revill. llvm-svn: 357470
* [RISCV] Support assembling %got_pcrel_hi operatorAlex Bradbury2019-02-151-0/+2
| | | | | | | Differential Revision: https://reviews.llvm.org/D55279 Patch by James Clarke. llvm-svn: 354110
* [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment ↵Shiva Chen2019-01-301-0/+2
| | | | | | | | | | | | | | | | | | | | when linker relaxation enabled Linker relaxation may change code size. We need to fix up the alignment of alignment directive in text section by inserting Nops and R_RISCV_ALIGN relocation type. So then linker could satisfy the alignment by removing Nops. To do this: 1. Add shouldInsertExtraNopBytesForCodeAlign target hook to calculate the Nops we need to insert. 2. Add shouldInsertFixupForCodeAlign target hook to insert R_RISCV_ALIGN fixup type. Differential Revision: https://reviews.llvm.org/D47755 llvm-svn: 352616
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [RISCV] Support linker relax function call from auipc and jalr to jalShiva Chen2018-05-241-0/+2
| | | | | | | | | | | | | To do this: 1. Add fixup_riscv_relax fixup types which eventually will transfer to R_RISCV_RELAX relocation types. 2. Insert R_RISCV_RELAX relocation types to auipc function call expression when linker relaxation enabled. Differential Revision: https://reviews.llvm.org/D44886 llvm-svn: 333158
* [RISCV] Add symbol diff relocation support for RISC-VAlex Bradbury2018-05-231-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For RISC-V it is desirable to have relaxation happen in the linker once addresses are known, and as such the size between two instructions/byte sequences in a section could change. For most assembler expressions, this is fine, as the absolute address results in the expression being converted to a fixup, and finally relocations. However, for expressions such as .quad .L2-.L1, the assembler folds this down to a constant once fragments are laid out, under the assumption that the difference can no longer change, although in the case of linker relaxation the differences can change at link time, so the constant is incorrect. One place where this commonly appears is in debug information, where the size of a function expression is in a form similar to the above. This patch extends the assembler to allow an AsmBackend to declare that it does not want the assembler to fold down this expression, and instead generate a pair of relocations that allow the linker to carry out the calculation. In this case, the expression is not folded, but when it comes to emitting a fixup, the generic FK_Data_* fixups are converted into a pair, one for the addition half, one for the subtraction, and this is passed to the relocation generating methods as usual. I have named these FK_Data_Add_* and FK_Data_Sub_* to indicate which half these are for. For RISC-V, which supports this via e.g. the R_RISCV_ADD64, R_RISCV_SUB64 pair of relocations, these are also set to always emit relocations relative to local symbols rather than section offsets. This is to deal with the fact that if relocations were calculated on e.g. .text+8 and .text+4, the result 12 would be stored rather than 4 as both addends are added in the linker. Differential Revision: https://reviews.llvm.org/D45181 Patch by Simon Cook. llvm-svn: 333079
* MC: Separate creating a generic object writer from creating a target object ↵Peter Collingbourne2018-05-211-6/+3
| | | | | | | | | | | | | writer. NFCI. With this we gain a little flexibility in how the generic object writer is created. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47045 llvm-svn: 332868
* [RISCV] Support "call" pseudoinstruction in the MC layerShiva Chen2018-04-251-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | To do this: 1. Add PseudoCALLIndirct to match indirect function call. 2. Add PseudoCALL to support parsing and print pseudo `call` in assembly 3. Expand PseudoCALL to the following form with R_RISCV_CALL relocation type while encoding: auipc ra, func jalr ra, ra, 0 If we expand PseudoCALL before emitting assembly, we will see auipc and jalr pair when compile with -S. It's hard for assembly parser to parsing this pair and identify it's semantic is function call and then insert R_RISCV_CALL relocation type. Although we could insert R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I relocation types instead of R_RISCV_CALL. Due to RISCV relocation design, auipc and jalr pair only can relax to jal with R_RISCV_CALL + R_RISCV_RELAX relocation types. We expand PseudoCALL as late as encoding(RISCVMCCodeEmitter) instead of before emitting assembly(RISCVAsmPrinter) because we want to preserve call pseudoinstruction in assembly code. It's more readable and assembly parser could identify call assembly and insert R_RISCV_CALL relocation type. Differential Revision: https://reviews.llvm.org/D45859 llvm-svn: 330826
* [RISCV] Add support for %pcrel_lo.Ahmed Charles2018-02-061-0/+4
| | | | llvm-svn: 324303
* [RISCV] MC layer support for the jump/branch instructions of the RVC extensionAlex Bradbury2017-12-071-0/+4
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40002 Patch by Shiva Chen. llvm-svn: 320038
* [RISCV] Bugfix createRISCVELFObjectWriterAlex Bradbury2017-10-181-1/+1
| | | | | | | r315275 set the IsLittleEndian parameter incorrectly. This patch corrects this, and adds a test to ensure such mistakes will be caught in the future. llvm-svn: 316091
* [RISCV] Fix build after r315327Alex Bradbury2017-10-111-2/+4
| | | | | | | Differential Revision: https://reviews.llvm.org/D38779 Patch by Chih-Mao Chen. llvm-svn: 315455
* [RISCV] Fix build after r315254Alex Bradbury2017-10-101-2/+3
| | | | | | | createELFObjectWriter now takes a std::unique_ptr<MCELFObjectTargetWriter> rather than a MCELFObjectTargetWriter*. llvm-svn: 315275
* [RISCV] Add common fixups and relocationsAlex Bradbury2017-09-281-1/+22
| | | | | | | | | | | | | %lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
* [RISCV] Fix two abuses of llvm_unreachableAlex Bradbury2017-08-201-1/+1
| | | | | | Replace with report_fatal_error. llvm-svn: 311276
* [RISCV] Set HasRelocationAddend for RISCVELFObjectWriterAlex Bradbury2017-08-201-1/+1
| | | | llvm-svn: 311275
* Removing a switch statement that contains a default label, but no case ↵Aaron Ballman2016-11-021-5/+1
| | | | | | labels. Silences an MSVC warning; NFC. llvm-svn: 285806
* [RISCV] Add bare-bones RISC-V MCTargetDescAlex Bradbury2016-11-011-0/+51
This is enough to compile and link but doesn't yet do anything particularly useful. Once an ASM parser and printer are added in the next two patches, the whole thing can be usefully tested. Differential Revision: https://reviews.llvm.org/D23562 llvm-svn: 285770
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