diff options
author | Alex Bradbury <asb@lowrisc.org> | 2016-11-01 23:47:30 +0000 |
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committer | Alex Bradbury <asb@lowrisc.org> | 2016-11-01 23:47:30 +0000 |
commit | 6b2cca7f8f37f4929328d970582892354a893f5a (patch) | |
tree | f90cfb4a844829deb2b2968b523141021f86775a /llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp | |
parent | 24d9b13b36bdd14a4bc7ad29f6715bd9ebbdfed8 (diff) | |
download | bcm5719-llvm-6b2cca7f8f37f4929328d970582892354a893f5a.tar.gz bcm5719-llvm-6b2cca7f8f37f4929328d970582892354a893f5a.zip |
[RISCV] Add bare-bones RISC-V MCTargetDesc
This is enough to compile and link but doesn't yet do anything particularly
useful. Once an ASM parser and printer are added in the next two patches, the
whole thing can be usefully tested.
Differential Revision: https://reviews.llvm.org/D23562
llvm-svn: 285770
Diffstat (limited to 'llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp')
-rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp new file mode 100644 index 00000000000..def20dd48e4 --- /dev/null +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp @@ -0,0 +1,51 @@ +//===-- RISCVELFObjectWriter.cpp - RISCV ELF Writer -----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/RISCVMCTargetDesc.h" +#include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/MC/MCFixup.h" +#include "llvm/Support/ErrorHandling.h" + +using namespace llvm; + +namespace { +class RISCVELFObjectWriter : public MCELFObjectTargetWriter { +public: + RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit); + + ~RISCVELFObjectWriter() override; + +protected: + unsigned getRelocType(MCContext &Ctx, const MCValue &Target, + const MCFixup &Fixup, bool IsPCRel) const override; +}; +} + +RISCVELFObjectWriter::RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit) + : MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_RISCV, + /*HasRelocationAddend*/ false) {} + +RISCVELFObjectWriter::~RISCVELFObjectWriter() {} + +unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx, + const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel) const { + // Determine the type of the relocation + switch ((unsigned)Fixup.getKind()) { + default: + llvm_unreachable("invalid fixup kind!"); + } +} + +MCObjectWriter *llvm::createRISCVELFObjectWriter(raw_pwrite_stream &OS, + uint8_t OSABI, bool Is64Bit) { + MCELFObjectTargetWriter *MOTW = new RISCVELFObjectWriter(OSABI, Is64Bit); + return createELFObjectWriter(MOTW, OS, /*IsLittleEndian*/ true); +} |