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* R600/SI: Teach SIInstrInfo::moveToVALU() how to handle PHI instructionsTom Stellard2014-04-171-3/+15
| | | | llvm-svn: 206498
* R600/SI: Legalize operands after changing dst reg in FixSGPRCopiesTom Stellard2014-04-171-2/+4
| | | | | | Otherwise we may not legalize some illegal REG_SEQUENCE instructions. llvm-svn: 206497
* R600/SI: f64 frint is legal on CIMatt Arsenault2014-04-172-2/+4
| | | | llvm-svn: 206475
* R600/SI: Fix zext from i1 to i64Matt Arsenault2014-04-171-2/+6
| | | | llvm-svn: 206437
* Convert SelectionDAG::getVTList to use ArrayRefCraig Topper2014-04-161-1/+1
| | | | llvm-svn: 206357
* R600: Expand sign extension of vectors.Matt Arsenault2014-04-164-16/+47
| | | | | | | | | | | | | | Setting vector types to expand will result in scalarization on pre SI hw, as those gpus don't have vector shifts either. Expand also i32 vectors, this helps llvm make the correct decision about scalarizing the vector ops. v2: move setOperation() calls to R600ISelLowering.cpp. cleanup the SI code to make it obvious that this patch does is nop for SI Patch by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 206348
* R600/SI: Print code size along with used registersMatt Arsenault2014-04-152-13/+19
| | | | llvm-svn: 206336
* R600/SI: Print more immediates in hex formatMatt Arsenault2014-04-154-13/+68
| | | | | | | | | Print in decimal for inline immediates, and hex otherwise. Use hex always for offsets in addressing offsets. This approximately matches what the shader compiler does. llvm-svn: 206335
* R600/SI: Cleanup parsing of register names.Matt Arsenault2014-04-152-34/+47
| | | | | | Try to figure out the class and number of subregisters. llvm-svn: 206334
* R600/SI: Fix loads of i1Matt Arsenault2014-04-152-4/+25
| | | | llvm-svn: 206330
* Break PseudoSourceValue out of the Value hierarchy. It is now the root of ↵Nick Lewycky2014-04-153-25/+39
| | | | | | its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead. llvm-svn: 206255
* R600: Check if a sextload should be used for parameter loads.Matt Arsenault2014-04-113-14/+20
| | | | | | | | | | Through some oddity where truncate (sextload x) isn't folded into an anyextload for vectors, the sextload remains if the vector isn't immediately scalarized. This keeps the expected zextload instructions in the kernel-args test when small type vectors aren't scalarized. llvm-svn: 206070
* R600/SI: Refactor SOPC classes slightly.Matt Arsenault2014-04-113-20/+28
| | | | | | | Better match what is done for VOPC to eventually prefer selecting these. llvm-svn: 206048
* Move ExtractVectorElements to SelectionDAG.Matt Arsenault2014-04-112-23/+6
| | | | | | | This seems generally useful, and makes sense to go along with SplitVector. llvm-svn: 206041
* Implement depth_first and inverse_depth_first range factory functions.David Blaikie2014-04-111-7/+5
| | | | | | | | | | | | | | Also updated as many loops as I could find using df_begin/idf_begin - strangely I found no uses of idf_begin. Is that just used out of tree? Also a few places couldn't use df_begin because either they used the member functions of the depth first iterators or had specific ordering constraints (I added a comment in the latter case). Based on a patch by Jim Grosbach. (Jim - you just had iterator_range<T> where you needed iterator_range<idf_iterator<T>>) llvm-svn: 206016
* LLVMBuild.txt: Add missing dependencies.NAKAMURA Takumi2014-04-101-1/+1
| | | | llvm-svn: 205962
* LLVMBuild.txt: Reformat.NAKAMURA Takumi2014-04-101-2/+2
| | | | llvm-svn: 205961
* R600/SI: Match not instruction.Matt Arsenault2014-04-092-1/+5
| | | | llvm-svn: 205837
* R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-04-072-0/+12
| | | | llvm-svn: 205732
* R600: Match 24-bit arithmetic patterns in a Target DAGCombineTom Stellard2014-04-0711-58/+115
| | | | | | | | | | | | | | | | | Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul llvm-svn: 205731
* R600: Replace dyn_cast + assert with castTom Stellard2014-04-071-2/+1
| | | | llvm-svn: 205730
* Use std::swapMatt Arsenault2014-04-071-3/+1
| | | | llvm-svn: 205723
* Use .data() instead of &x[0]Matt Arsenault2014-04-072-18/+21
| | | | llvm-svn: 205722
* MachineInstr: introduce explicit_operands and implicit_operands rangesDavid Blaikie2014-04-051-3/+1
| | | | | | | Makes iteration over implicit and explicit machine operands more explicit (har har). Insipired by code review discussion for r205565. llvm-svn: 205680
* Fix tabsMatt Arsenault2014-04-041-5/+5
| | | | llvm-svn: 205648
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-042-5/+5
| | | | llvm-svn: 205610
* R600: Correct opcode for BFE_INTTom Stellard2014-04-031-1/+1
| | | | | | | | | | | Acording to AMD documentation, the correct opcode for BFE_INT is 0x5, not 0x4 Fixes Arithm/Absdiff.Mat/3 OpenCV test Patch by: Bruno Jiménez llvm-svn: 205562
* R600/SI: Lower 64-bit immediates using REG_SEQUENCETom Stellard2014-04-034-19/+43
| | | | llvm-svn: 205561
* R600/SI: Remove leftover pattern splitting 64-bit ors.Matt Arsenault2014-03-311-8/+0
| | | | | | | It's now matched to the scalar 64-bit or and split later if necessary.' llvm-svn: 205252
* Change shouldSplitVectorElementType to better match the description.Matt Arsenault2014-03-312-3/+3
| | | | | | Pass the entire vector type, and not just the element. llvm-svn: 205247
* R600/SI: Implement shouldConvertConstantLoadToIntImmMatt Arsenault2014-03-314-18/+37
| | | | llvm-svn: 205244
* R600: Compute masked bits for min and maxMatt Arsenault2014-03-311-0/+44
| | | | llvm-svn: 205242
* R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.Matt Arsenault2014-03-313-1/+33
| | | | llvm-svn: 205236
* R600: Add target nodes for BFM and BFIMatt Arsenault2014-03-315-3/+14
| | | | llvm-svn: 205235
* R600/SI: Implement SIInstrInfo::isTriviallyRematerializable()Tom Stellard2014-03-312-0/+15
| | | | llvm-svn: 205188
* R600/SI: Lower i64 SELECT by bitcasting to a vector typeTom Stellard2014-03-312-7/+10
| | | | | | | This allows allows us to replace ISD::EXTRACT_ELEMENT, which is lowered using shifts, with ISD::EXTRACT_VECTOR_ELT, which is a no-op. llvm-svn: 205187
* R600/SI: Return the correct index for VGPRs in getHWRegIndex()Tom Stellard2014-03-311-1/+1
| | | | | | The register index is stored in the low 8-bits of the encoding. llvm-svn: 205186
* Completely rewrite ELFObjectWriter::RecordRelocation.Rafael Espindola2014-03-291-7/+7
| | | | | | | | | | | | | | | | | | | I started trying to fix a small issue, but this code has seen a small fix too many. The old code was fairly convoluted. Some of the issues it had: * It failed to check if a symbol difference was in the some section when converting a relocation to pcrel. * It failed to check if the relocation was already pcrel. * The pcrel value computation was wrong in some cases (relocation-pc.s) * It was missing quiet a few cases where it should not convert symbol relocations to section relocations, leaving the backends to patch it up. * It would not propagate the fact that it had changed a relocation to pcrel, requiring a quiet nasty work around in ARM. * It was missing comments. llvm-svn: 205076
* R600: avoid calling std::next on an iterator that might be end()Tim Northover2014-03-281-3/+3
| | | | | | | | This was causing my llc to go into an infinite loop on CodeGen/R600/address-space.ll (just triggered recently by some allocator changes). llvm-svn: 205005
* Remove another unused argument.Rafael Espindola2014-03-271-1/+1
| | | | llvm-svn: 204961
* Remove unused argument.Rafael Espindola2014-03-271-3/+2
| | | | llvm-svn: 204956
* R600: Implement isZExtFree.Matt Arsenault2014-03-272-0/+20
| | | | | | | This allows 64-bit operations that are truncated to be reduced to 32-bit ones. llvm-svn: 204946
* R600/SI: Fix unreachable with a sext_in_reg to an illegal type.Matt Arsenault2014-03-274-4/+28
| | | | llvm-svn: 204945
* R600: Add a testcase for sext_in_reg I missed.Matt Arsenault2014-03-261-0/+2
| | | | | | This sext_inreg i32 in i64 case was already handled, but not enabled. llvm-svn: 204840
* R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cppMatt Arsenault2014-03-253-39/+12
| | | | | | | | Remove handling of select_cc, since it makes no sense to be there. This now does nothing, but I'll be adding some handling of other target nodes soon. llvm-svn: 204743
* R600: Don't viewCFG() under DEBUG() except on failure.Matt Arsenault2014-03-241-9/+6
| | | | | | | Having these popping up every time you use -debug is really irritating. llvm-svn: 204664
* R600/SI: Fix extra mov from legalizing 64-bit SALU ops.Matt Arsenault2014-03-241-14/+26
| | | | | | | Check the register class of each operand individually to avoid an extra copy to a vgpr. llvm-svn: 204662
* R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.Matt Arsenault2014-03-242-17/+44
| | | | | | | No longer asserts, but now you get moves loading legal immediates into the split 32-bit operations. llvm-svn: 204661
* R600/SI: Fix 64-bit bit ops that require the VALU.Matt Arsenault2014-03-243-1/+82
| | | | | | | | Try to match scalar and first like the other instructions. Expand 64-bit ands to a pair of 32-bit ands since that is not available on the VALU. llvm-svn: 204660
* R600: Implement isNarrowingProfitable.Matt Arsenault2014-03-242-0/+12
| | | | llvm-svn: 204658
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