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path: root/llvm/lib/Target/R600/SIInstructions.td
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* R600 -> AMDGPU renameTom Stellard2015-06-131-3327/+0
| | | | llvm-svn: 239657
* R600/SI: Move flat instruction defs to CIInstructions.tdTom Stellard2015-06-111-108/+0
| | | | llvm-svn: 239534
* R600: Switch to using generic min / max nodes.Matt Arsenault2015-06-091-4/+4
| | | | llvm-svn: 239377
* R600/SI: Add assembler support for all CI and VI VOP2 instructionsTom Stellard2015-05-261-0/+8
| | | | llvm-svn: 238211
* R600/SI: Remove some unnecessary patterns from VINTRP multiclassTom Stellard2015-05-251-3/+5
| | | | | | | DisableEncoding and Constraints can be set using let statements around the multiclass defs. llvm-svn: 238148
* R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chipsTom Stellard2015-05-251-3/+20
| | | | | | The src and dst register cannot be the same on chips with 16 lds banks. llvm-svn: 238147
* R600/SI: Use NAME rather than opName as the key to the MCOpcode tablesTom Stellard2015-05-251-3/+3
| | | | | | | | This lets us drop a parameter the opName parameter to the VINTRP multiclass and makes it possible to create multiple VINTRP defs with the same asm mnemonic. llvm-svn: 238146
* R600/SI: Fix bug in VGPR spillingTom Stellard2015-05-121-2/+2
| | | | | | | | | | | | AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which caused the srsrc and soffset register to not be set correctly. This commit replaces the switch statement with a SITargetInfo query to make sure all spill instructions are covered. Differential Revision: http://reviews.llvm.org/D9582 llvm-svn: 237164
* R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0Tom Stellard2015-05-121-1/+4
| | | | | | | | We had code to do this in SIRegisterInfo::eliminateFrameIndex(), but it is easier to just change the definition of SI_SPILL_S32_RESTORE to only allow numbered sgprs. llvm-svn: 237143
* R600/SI: Remove explicit m0 operand from DS instructionsTom Stellard2015-05-121-48/+48
| | | | | | | Instead add m0 as an implicit operand. This helps avoid spills of the m0 register in some cases. llvm-svn: 237141
* R600/SI: Remove explicit m0 operand from v_interp instructionsTom Stellard2015-05-121-30/+17
| | | | | | | Instead add m0 as an implicit operand. This helps avoid spills of the m0 register in some cases. llvm-svn: 237140
* R600/SI: Remove explicit m0 operand from s_sendmsgTom Stellard2015-05-121-7/+5
| | | | | | | | | | | | | | | Instead add m0 as an implicit operand. This allows us to avoid using the M0Reg register class and eliminates a number of unnecessary spills when using s_sendmsg instructions. This impacts one shader in the shader-db: SGPRS: 48 -> 40 (-16.67 %) VGPRS: 112 -> 108 (-3.57 %) Code Size: 40132 -> 38796 (-3.33 %) bytes LDS: 0 -> 0 (0.00 %) blocks Scratch: 2048 -> 0 (-100.00 %) bytes per wave llvm-svn: 237133
* R600/SI: Add VCC as an implict def of SI_KILLTom Stellard2015-05-011-3/+6
| | | | | | When SI_KILL has a register operand, its lowered form writes to vcc. llvm-svn: 236307
* R600/RegisterCoalescer: Enable more rematerialization/add missing testcaseMatthias Braun2015-04-241-2/+2
| | | | | | | This enables the rematerialization of some R600 MOV instructions in the RegisterCoalescer and adds a testcase for r235668. llvm-svn: 235675
* R600/SI: v_mov_fed_b32 does not exist on VITom Stellard2015-04-231-1/+1
| | | | llvm-svn: 235628
* R600/SI: Initial support for assembler and inline assemblyTom Stellard2015-04-081-12/+3
| | | | | | | | | | | | | This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
* R600/SI: Add missing SOPK instructionsTom Stellard2015-04-081-9/+19
| | | | llvm-svn: 234380
* R600/SI: Select V_BFE_U32 for and+shift with a non-literal offsetMarek Olsak2015-03-241-0/+2
| | | | llvm-svn: 233079
* R600/SI: Improve BFM supportMarek Olsak2015-03-241-3/+19
| | | | llvm-svn: 233077
* R600/SI: Use V_FRACT_F64 for faster 64-bit floor on SIMarek Olsak2015-03-241-0/+51
| | | | | | | Other f64 opcodes not supported on SI can be lowered in a similar way. v2: use complex VOP3 patterns llvm-svn: 233076
* R600/SI: Expand fract to floor, then only select V_FRACT on CIMarek Olsak2015-03-241-0/+22
| | | | | | | | | V_FRACT is buggy on SI. R600-specific code is left intact. v2: drop the multiclass, use complex VOP3 patterns llvm-svn: 233075
* R600/SI: Only use one range of isCommutable for comparesMatt Arsenault2015-03-231-38/+2
| | | | | | Also don't count the class instructions as isCompare anymore. llvm-svn: 232991
* R600/SI: Remove redundant unsetting of hasSideEffectsMatt Arsenault2015-03-231-2/+0
| | | | | | These are already set in the base class for the instruction. llvm-svn: 232990
* R600/SI: Move hasSideEffects setting into VOPCX classesMatt Arsenault2015-03-231-23/+17
| | | | llvm-svn: 232989
* R600/SI: Allow commuting comparesMatt Arsenault2015-03-231-61/+77
| | | | | | | | | | | | | | | | | This enables very common cases to switch to the smaller encoding. All of the standard LLVM canonicalizations of comparisons are the opposite of what we want. Compares with constants are moved to the RHS, but the first operand can be an inline immediate, literal constant, or SGPR using the 32-bit VOPC encoding. There are additional bad canonicalizations that should also be fixed, such as canonicalizing ge x, k to gt x, (k + 1) if this makes k no longer an inline immediate value. llvm-svn: 232988
* R600/SI: Use right class for cmpsx f64 instructionsMatt Arsenault2015-03-231-20/+20
| | | | | | Use VOPCX_F64 to not need the let Defs = [EXEC] llvm-svn: 232987
* [Tablegen] Attempt to add support for patterns containing nodes with ↵Craig Topper2015-03-201-6/+6
| | | | | | | | | | multiple results. This is needed for AVX512 masked scatter/gather support. The R600 change is necessary to remove a hack that was working around the lack of multiple results. llvm-svn: 232798
* R600/SI: Remove _e32 and _e64 suffixes from mnemonicsTom Stellard2015-03-121-1/+1
| | | | | | | | Instead print them as part of the $dst operand. The AsmMatcher requires the 32-bit and 64-bit encodings have the same mnemonic in order to parse them correctly. llvm-svn: 232105
* R600/SI: Re-order MUBUF operands to match asm strings.Tom Stellard2015-03-101-8/+8
| | | | llvm-svn: 231797
* R600/SI: Add 32-bit encoding of v_cndmask_b32Tom Stellard2015-03-101-6/+15
| | | | | | | This was done by refactoring the v_cndmask_b32 tablegen definition to use inherit from VOP2Inst. llvm-svn: 231795
* R600/SI: Move gds operand to the end of operand listTom Stellard2015-03-091-9/+9
| | | | | | Also print it in the assembly string. llvm-svn: 231684
* R600/SI: Refactor DS instruction defsTom Stellard2015-03-091-19/+29
| | | | llvm-svn: 231683
* R600/SI: Fix DS definitions and add missing instructionsTom Stellard2015-03-091-42/+79
| | | | llvm-svn: 231663
* R600/SI: Fix opcode for ds_read2_b64 and ds_read2st64_b64Tom Stellard2015-03-091-2/+2
| | | | llvm-svn: 231662
* R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32Marek Olsak2015-03-041-1/+3
| | | | | | Required by OpenGL (ARB_gpu_shader5). llvm-svn: 231259
* R600/SI: Add missing mubuf instructionsTom Stellard2015-02-271-8/+24
| | | | llvm-svn: 230759
* R600/SI: Consistently put soffset before the offset operand for mubuf ↵Tom Stellard2015-02-271-3/+3
| | | | | | | | instructions This matches the assembly syntax. llvm-svn: 230758
* R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructionsTom Stellard2015-02-271-2/+3
| | | | llvm-svn: 230757
* R600/SI: Fix mad*k definitionsMatt Arsenault2015-02-211-2/+2
| | | | llvm-svn: 230146
* R600/SI: Remove v_sub_f64 pseudoMatt Arsenault2015-02-201-11/+0
| | | | | | | | | | The expansion code does the same thing. Since the operands were not defined with the correct types, this has the side effect of fixing operand folding since the expanded pseudo would never use SGPRs or inline immediates. llvm-svn: 230072
* R600: Use new fmad node.Matt Arsenault2015-02-201-3/+0
| | | | | | | | | | | This enables a few useful combines that used to only use fma. Also since v_mad_f32 apparently does not support denormals, disable the existing cases that are custom handled if they are requested. llvm-svn: 230071
* R600/SI: Fix READLANE and WRITELANE lane select for VIMarek Olsak2015-02-181-4/+4
| | | | | | | | | | | | VOP2 declares vsrc1, but VOP3 declares src1. We can't use the same "ins" if the operands have different names in VOP2 and VOP3 encodings. This fixes a hang in geometry shaders which spill M0 on VI. (BTW it doesn't look like M0 needs spilling and the spilling seems duplicated 3 times) llvm-svn: 229752
* R600/SI: Add missing VOP1 instructionsTom Stellard2015-02-181-5/+15
| | | | llvm-svn: 229688
* R600/SI: Add missing VOP2 instructionsTom Stellard2015-02-181-2/+9
| | | | llvm-svn: 229687
* R600/SI: Add definition for S_CBRANCH_G_FORKTom Stellard2015-02-181-1/+7
| | | | llvm-svn: 229686
* R600/SI: Add missing SOP1 instructionsTom Stellard2015-02-181-12/+12
| | | | llvm-svn: 229685
* R600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64Matt Arsenault2015-02-181-1/+1
| | | | | | | Rename the multiclass since it now applies to the output modifiers as well. llvm-svn: 229610
* R600/SI: Add missing offset operand to buffer bothenMatt Arsenault2015-02-181-2/+2
| | | | llvm-svn: 229605
* R600/SI: Implement correct f64 fdivMatt Arsenault2015-02-141-10/+7
| | | | | | This version passes the OpenCL conformance test. llvm-svn: 229239
* R600/SI: Fix implicit vcc operand to v_div_fmas_*Matt Arsenault2015-02-141-3/+16
| | | | | | | | | This should allow finally fixing the f64 fdiv implementation. Test is disabled for VI since there seems to be a problem with one of the buffer load instructions on it. llvm-svn: 229236
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