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path: root/llvm/lib/Target/R600/SIInstructions.td
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* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-94/+94
* R600/SI: Add a V_MOV_B64 pseudo instructionTom Stellard2015-01-071-0/+6
* R600/SI: Add class intrinsicMatt Arsenault2015-01-061-4/+4
* R600/SI: Fix f64 inline immediatesMatt Arsenault2014-12-171-0/+5
* R600: Fix min/max matching problems with unordered comparesMatt Arsenault2014-12-121-0/+2
* R600/SI: Don't promote f32 select to i32Matt Arsenault2014-12-121-0/+5
* R600/SI: Use unordered equal instructionsMatt Arsenault2014-12-111-2/+2
* R600/SI: Make more unordered comparisons legalMatt Arsenault2014-12-111-8/+8
* R600/SI: Use unordered not equal instructionsMatt Arsenault2014-12-111-2/+2
* R600/SI: Set 20-bit immediate byte offset for SMRD on VIMarek Olsak2014-12-071-1/+41
* R600/SI: Add VI instructionsMarek Olsak2014-12-071-490/+520
* R600/SI: Add SCC Defs/Uses to SOP1 and SOP2 opcodesMarek Olsak2014-12-071-28/+49
* R600/SI: Remove i1 pseudo VALU opsMatt Arsenault2014-12-031-23/+30
* Revert r222746: That commit did not update any tests and caused two R600Chandler Carruth2014-11-251-2/+1
* R600/SI: Disable commutativity for MIN/MAX_LEGACYMarek Olsak2014-11-251-1/+2
* R600/SI: Add an s_mov_b32 to patterns which use the M0RegClassTom Stellard2014-11-211-4/+8
* R600/SI: Emit s_mov_b32 m0, -1 before every DS instructionTom Stellard2014-11-211-7/+8
* R600/SI: Mark s_mov_b32 and s_mov_b64 as rematerializableTom Stellard2014-11-211-0/+2
* R600/SI: Mark s_movk_i32 as rematerializableTom Stellard2014-11-141-0/+2
* R600/SI: Combine min3/max3 instructionsMatt Arsenault2014-11-141-9/+21
* R600/SI: Use S_BFE_I64 for 64-bit sext_inregMatt Arsenault2014-11-141-14/+9
* R600/SI: Start implementing an assemblerTom Stellard2014-11-141-25/+30
* R600/SI: Fix fmin_legacy / fmax_legacy matching for SIMatt Arsenault2014-11-131-2/+2
* R600/SI: Fix definition for s_cselect_b32Matt Arsenault2014-11-131-3/+2
* R600/SI: Get rid of FCLAMP_SI pseudoMatt Arsenault2014-11-131-11/+3
* R600/SI: Allow commuting some 3 op instructionsMatt Arsenault2014-11-131-3/+27
* R600/SI: Remove SI_ADDR64_RSRCMatt Arsenault2014-11-051-8/+0
* R600/SI: Change all instruction assembly names to lowercase.Tom Stellard2014-11-051-856/+856
* R600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGsMatt Arsenault2014-11-021-41/+35
* Support REG_SEQUENCE in tablegen.Matt Arsenault2014-11-021-3/+3
* Add minnum / maxnum codegenMatt Arsenault2014-10-211-4/+5
* R600/SI: Add pattern for bswapMatt Arsenault2014-10-211-0/+7
* R600/SI: Add global atomicrmw xchgAaron Watry2014-10-171-0/+3
* R600/SI: Add global atomicrmw xorAaron Watry2014-10-171-1/+3
* R600/SI: Add global atomicrmw orAaron Watry2014-10-171-1/+3
* R600/SI: Add global atomicrmw min/uminAaron Watry2014-10-171-2/+6
* R600/SI: Add global atomicrmw max/umaxAaron Watry2014-10-171-2/+6
* R600/SI: Add global atomicrmw andAaron Watry2014-10-171-1/+3
* R600/SI: Add global atomicrmw subAaron Watry2014-10-171-1/+3
* R600/SI: Remove redundant setting of instruction bitsMatt Arsenault2014-10-171-4/+0
* R600/SI: Use complex pattern for MUBUF load patterns.Matt Arsenault2014-10-171-3/+2
* R600/SI: Remove SI_BUFFER_RSRC pseudoMatt Arsenault2014-10-171-6/+0
* R600/SI: Remove another VALU patternMatt Arsenault2014-10-161-5/+0
* R600/SI: Remove unnecessary VALU patternsMatt Arsenault2014-10-161-41/+0
* R600/SI: Refactor VOP3 instruction defsTom Stellard2014-10-071-47/+47
* R600/SI: Refactor VOPC instruction defsTom Stellard2014-10-071-196/+196
* R600/SI: Refactor VOP2 instruction defsTom Stellard2014-10-071-35/+34
* R600/SI: Refactor VOP1 instruction defsTom Stellard2014-10-071-57/+56
* R600/SI: Add a generic pseudo EXP instructionTom Stellard2014-10-011-0/+6
* R600/SI: Add generic pseudo MTBUF instructionsTom Stellard2014-10-011-5/+5
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