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* Add saving and restoring of r30 to the prologue and epilogue, respectivelyJustin Hibbits2015-01-082-0/+17
* Fix large stack alignment codegen for ARM and Thumb2 targetsKristof Beyls2015-01-082-22/+84
* R600/SI: Remove SIISelLowering::legalizeOperands()Tom Stellard2015-01-082-176/+1
* [X86] Don't try to generate direct calls to TLS globalsMichael Kuperstein2015-01-081-1/+2
* [X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LE...Craig Topper2015-01-084-4/+14
* [SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha2015-01-0815-136/+190
* X86: VZeroUpperInserter: shortcut should not trigger if we have any function ...Matthias Braun2015-01-081-8/+12
* R600/SI: Commute instructions to enable more folding opportunitiesTom Stellard2015-01-072-19/+51
* R600/SI: Only fold immediates that have one useTom Stellard2015-01-071-1/+8
* [CodeGen] Use MVT iterator_ranges in legality loops. NFC intended.Ahmed Bougacha2015-01-076-84/+45
* R600/SI: Remove VReg_32 register classTom Stellard2015-01-0713-154/+152
* [Hexagon] Fix 225372 USR register is not fully complete. Removing Uses = [US...Colin LeMahieu2015-01-071-12/+12
* [Hexagon] Adding floating point classification and creation.Colin LeMahieu2015-01-071-0/+45
* R600/SI: Add a V_MOV_B64 pseudo instructionTom Stellard2015-01-073-0/+38
* [Hexagon] Adding encodings for v5 floating point instructions.Colin LeMahieu2015-01-071-0/+326
* [Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding.Colin LeMahieu2015-01-072-1/+62
* R600/SI: Teach SIFoldOperands to split 64-bit constants when foldingTom Stellard2015-01-073-25/+51
* [X86] Fix 512->256 typo in comments. NFC.Ahmed Bougacha2015-01-071-2/+2
* X86: Allow the stack probe size to be configurable per functionDavid Majnemer2015-01-071-3/+9
* R600/SI: Refactor SIFoldOperands to simplify immediate foldingTom Stellard2015-01-071-25/+54
* [X86] Teach FCOPYSIGN lowering to recognize constant magnitudes.Ahmed Bougacha2015-01-071-6/+19
* Fix regression in r225266.Asiri Rathnayake2015-01-071-1/+1
* [X86] Merge a switch statement inside a default case of another switch statem...Craig Topper2015-01-071-160/+155
* [X86] Don't mark the shift by 1 instructions as isConvertibleToThreeAddress. ...Craig Topper2015-01-071-1/+1
* [X86] Remove some unused TYPE enums from the disassembler.Craig Topper2015-01-073-18/+1
* Revert r225165 and r225169Karthik Bhat2015-01-071-39/+0
* R600/SI: Add check for amdgcn triple forgotten in r225276.Tom Stellard2015-01-071-2/+3
* [PowerPC] Transform a README.txt entry into a FIXMEHal Finkel2015-01-072-14/+9
* Revert r224935 "Refactor duplicated code. No intended functionality change."Lang Hames2015-01-066-8/+30
* R600/SI: Add combine for isinfinite patternMatt Arsenault2015-01-062-0/+57
* R600/SI: Pattern match isinf to v_cmp_class instructionsMatt Arsenault2015-01-062-0/+34
* R600/SI: Add basic DAG combines for fp_classMatt Arsenault2015-01-062-1/+50
* R600/SI: Add class intrinsicMatt Arsenault2015-01-067-5/+82
* [PowerPC] Reuse a load operand in int->fp conversionsHal Finkel2015-01-063-41/+142
* [Hexagon] Adding compound jump encodings.Colin LeMahieu2015-01-062-0/+266
* R600/SI: Insert s_waitcnt before s_barrier instructions.Tom Stellard2015-01-061-1/+5
* R600/SI: Fix dependency calculation for DS writes instructions in SIInsertWaitsTom Stellard2015-01-061-0/+23
* [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dc...Colin LeMahieu2015-01-063-1/+101
* [Hexagon] Adding encoding information for absolute address loads.Colin LeMahieu2015-01-061-124/+186
* R600/SI: Add a stub GCNTargetMachineTom Stellard2015-01-068-1/+46
* R600/SI: Remove MachineFunction dump from AsmPrinterTom Stellard2015-01-061-17/+12
* [Hexagon] Fix 225267. GP register is not yet fully implemented. Removing Us...Colin LeMahieu2015-01-061-2/+2
* [Hexagon] Adding dealloc_return encoding and absolute address stores.Colin LeMahieu2015-01-065-239/+347
* [ARM] Cleanup so_imm* tblgen defintionsAsiri Rathnayake2015-01-062-109/+43
* [X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.Craig Topper2015-01-064-7/+40
* [X86] Make isel select the 2-byte register form of INC/DEC even in non-64-bit...Craig Topper2015-01-065-126/+78
* [PowerPC] Remove old README.txt entry regarding struct passingHal Finkel2015-01-061-8/+0
* X86: Don't make illegal GOTTPOFF relocationsDavid Majnemer2015-01-062-0/+17
* [PowerPC] Add some missing names in getTargetNodeNameHal Finkel2015-01-061-0/+7
* [PowerPC] Improve int_to_fp(fp_to_int(x)) combiningHal Finkel2015-01-062-30/+74
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