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path: root/llvm/lib/Target/R600/SIInstrInfo.cpp
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* R600/SI: Implement areMemAccessesTriviallyDisjointMatt Arsenault2014-11-191-0/+83
| | | | | | | | | This partially makes up for not having address spaces used for alias analysis in some simple cases. This is not yet enabled by default so shouldn't change anything yet. llvm-svn: 222286
* R600/SI: Don't copy flags when extracting subregMatt Arsenault2014-11-171-6/+8
| | | | | | | | | This was resulting in use of a register after a kill. For some reason this showed up as a problem in many tests when moving the SIFixSGPRCopies pass closer to instruction selection. llvm-svn: 222175
* Fix unused variable warning without assertsMatt Arsenault2014-11-141-0/+2
| | | | llvm-svn: 222017
* R600/SI: Use S_BFE_I64 for 64-bit sext_inregMatt Arsenault2014-11-141-1/+65
| | | | llvm-svn: 222012
* R600/SI: Allow commuting with src2_modifiersMatt Arsenault2014-11-131-5/+0
| | | | llvm-svn: 221911
* Fix typoMatt Arsenault2014-10-171-1/+1
| | | | llvm-svn: 220068
* R600/SI: Allow commuting with source modifiersMatt Arsenault2014-10-171-11/+22
| | | | llvm-svn: 220066
* R600/SI: Fix general commuting breaking src modsMatt Arsenault2014-10-171-1/+13
| | | | | | | | The generic code trying to use findCommutedOpIndices won't understand that it needs to swap the modifier operands also, so it should fail if they are set. llvm-svn: 220064
* R600/SI: Allow comuting fp immediatesMatt Arsenault2014-10-171-3/+9
| | | | llvm-svn: 220062
* R600/SI: Use early return instead of checking condition twiceMatt Arsenault2014-10-171-11/+16
| | | | | | Any commutable instruction will have at least src1. llvm-svn: 220061
* R600/SI: Minor cleanup of functionMatt Arsenault2014-10-131-9/+11
| | | | llvm-svn: 219616
* R600/SI: Remove assertion in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2014-10-071-1/+4
| | | | | | | Added a FIXME coment instead, we need to handle the case where the two DS instructions being compared have different numbers of operands. llvm-svn: 219236
* R600/SI: Update VOP3b to not include obsolete operandsMatt Arsenault2014-09-301-4/+2
| | | | | | abs / neg are now part of the srcN_modifiers operands llvm-svn: 218691
* R600/SI: Use break instead of continueMatt Arsenault2014-09-261-1/+1
| | | | | | If an instruction doesn't have src1, it doesn't have src2 llvm-svn: 218536
* R600/SI: Move finding SGPR operand to move to separate functionMatt Arsenault2014-09-261-63/+69
| | | | llvm-svn: 218533
* R600/SI Allow same SGPR to be used for multiple operandsMatt Arsenault2014-09-261-5/+32
| | | | | | | | | | | Instead of moving the first SGPR that is different than the first, legalize the operand that requires the fewest moves if one SGPR is used for multiple operands. This saves extra moves and is also required for some instructions which require that the same operand be used for multiple operands. llvm-svn: 218532
* R600/SI: Partially move operand legalization to post-isel hook.Matt Arsenault2014-09-261-10/+29
| | | | | | | | | Disable the SGPR usage restriction parts of the DAG legalizeOperands. It now should only be doing immediate folding until it can be replaced later. The real legalization work is now done by the other SIInstrInfo::legalizeOperands llvm-svn: 218531
* R600/SI: Implement findCommutedOpIndicesMatt Arsenault2014-09-261-0/+32
| | | | | | | | | | | The base implementation of commuteInstruction is used in some cases, but it turns out this has been broken for a long time since modifiers were inserted between the real operands. The base implementation of commuteInstruction also fails on immediates, which also needs to be fixed. llvm-svn: 218530
* R600/SI: Don't move operands that are required to be SGPRsMatt Arsenault2014-09-261-1/+20
| | | | | | | | e.g. v_cndmask_b32 requires the condition operand be an SGPR. If one of the source operands were an SGPR, that would be considered the one SGPR use and the condition operand would be illegally moved. llvm-svn: 218529
* R600/SI: Don't assert on exotic operand typesMatt Arsenault2014-09-261-1/+1
| | | | | | | | | This needs a test, but I'm not sure if it is currently possible and I originally hit it due to a bug. Right now the only global address operands have no reason to be VALU instructions, although it theoretically could be a problem. llvm-svn: 218528
* R600/SI: Fix using wrong operand indices when commutingMatt Arsenault2014-09-261-11/+20
| | | | | | | | | | | | | No test since the current SIISelLowering::legalizeOperands effectively hides this, and the general uses seem to only fire on SALU instructions which don't have modifiers between the operands. When trying to use legalizeOperands immediately after instruction selection, it now sees a lot more patterns it did not see before which break on this. llvm-svn: 218527
* Silencing an "enumeral and non-enumeral type in conditional expression" ↵Aaron Ballman2014-09-241-1/+2
| | | | | | warning. NFC. llvm-svn: 218381
* R600/SI: Fix hardcoded and wrong operand numbers.Matt Arsenault2014-09-241-5/+3
| | | | | | Also fix leftover debug printing llvm-svn: 218359
* R600/SI: Fix the FixSGPRLiveRanges passTom Stellard2014-09-241-0/+4
| | | | | | | | | | | The previous implementation was extending the live range of SGPRs by modifying the live intervals directly. This was causing a lot of machine verification errors when the machine scheduler was enabled. The new implementation adds pseudo instructions with implicit uses to extend the live ranges of SGPRs, which works much better. llvm-svn: 218351
* R600/SI: Implement VGPR register spilling for compute at -O0 v3Tom Stellard2014-09-241-28/+158
| | | | | | | | | | | | | | VGPRs are spilled to LDS. This still needs more testing, but we need to at least enable it at -O0, because the fast register allocator spills all registers that are live at the end of blocks and without this some future commits will break the flat-address-space.ll test. v2: Only calculate thread id once v3: Move insertion of spill instructions to SIRegisterInfo::eliminateFrameIndex() llvm-svn: 218348
* R600/SI: Clean up checks for legality of immediate operandsTom Stellard2014-09-231-35/+59
| | | | | | | | | | | | | | There are new register classes VCSrc_* which represent operands that can take an SGPR, VGPR or inline constant. The VSrc_* class is now used to represent operands that can take an SGPR, VGPR, or a 32-bit immediate. This allows us to have more accurate checks for legality of immediates, since before we had no way to distinguish between operands that supported any 32-bit immediate and operands which could only support inline constants. llvm-svn: 218334
* Fix typoMatt Arsenault2014-09-231-2/+3
| | | | llvm-svn: 218324
* R600/SI: Remove assertMatt Arsenault2014-09-171-6/+7
| | | | | | | | | | Since read2 / write2 are emitted for 4-byte aligned 8-byte accesses, these are seen by the scheduler. The DAG scheduler is semi-deprecated, so just ignore these for now. llvm-svn: 217969
* R600/SI: Rough first implementation of shouldClusterLoadsMatt Arsenault2014-09-171-0/+22
| | | | llvm-svn: 217968
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-0/+8
| | | | llvm-svn: 217777
* R600/SI: Report offset in correct units for st64 DS instructionsMatt Arsenault2014-09-101-0/+15
| | | | | | | | | | | Need to convert the 64 element offset into bytes, not just the element size like the normal case instructions. Noticed by inspection. This can't be hit now because st64 instructions aren't emitted during instruction selection, and the post-RA scheduler isn't enabled. llvm-svn: 217560
* R600/SI: Fix bug in SIInstrInfo::legalizeOpWithMove()Tom Stellard2014-09-051-4/+5
| | | | | | | | | | We must constrain the destination register class of legalized operands to a VGPR class or else the illegal operand may be folded back into the instruction by the register coalescer. This fixes a bug in add.ll that will be uncovered by future commits. llvm-svn: 217249
* R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of 64-bit operationsTom Stellard2014-09-051-3/+5
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=83416 llvm-svn: 217248
* R600/SI: Try to keep i32 mul on SALUMatt Arsenault2014-09-031-0/+5
| | | | | | | Also fix bug this exposed where when legalizing an immediate operand, a v_mov_b32 would be created with a VSrc dest register. llvm-svn: 217108
* R600/SI: Fix typos in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2014-09-031-2/+2
| | | | | | | | | | This fixes a crash in the OpenCV test: ImgprocWarpResizeArea/Resize.Mat/16 There is no test case for this, because this failure depends on a specific ordering of the loads, which could easily change. llvm-svn: 217040
* R600/SI: Teach moveToVALU how to handle more S_LOAD_* instructionsTom Stellard2014-08-211-9/+121
| | | | llvm-svn: 216220
* R600/SI: Use eliminateFrameIndex() to expand SGPR spill pseudosTom Stellard2014-08-211-98/+11
| | | | | | | | | | | | | | | This will simplify the SGPR spilling and also allow us to use MachineFrameInfo for calculating offsets, which should be more reliable than our custom code. This fixes a crash in some cases where a register would be spilled in a branch such that the VGPR defined for spilling did not dominate all the uses when restoring. This fixes a crash in an ocl conformance test. The test requries register spilling and is too big to include. llvm-svn: 216217
* R600/SI: Fix offset folding in some cases with shifted pointers.Matt Arsenault2014-08-151-0/+22
| | | | | | | | | | | | | Ordinarily (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) is only done if the add has one use. If the resulting constant add can be folded into an addressing mode, force this to happen for the pointer operand. This ends up happening a lot because of how LDS objects are allocated. Since the globals are allocated next to each other, acessing the first element of the second object is directly indexed by a shifted pointer. llvm-svn: 215739
* R600/SIInstrInfo.cpp: Suppress an warning. [-Wunused-variable]NAKAMURA Takumi2014-08-111-0/+1
| | | | llvm-svn: 215406
* R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variantTom Stellard2014-08-111-103/+156
| | | | | | | This saves us from having to copy a 64-bit 0 value into VGPRs for BUFFER_* instruction which only have a 12-bit immediate offset. llvm-svn: 215399
* R600/SI: Implement areLoadsFromSameBasePtrMatt Arsenault2014-08-061-0/+98
| | | | | | | | This currently has a noticable effect on the kernel argument loads. LDS and global loads are more problematic, I think because of how copies are currently inserted to ensure that the address is a VGPR. llvm-svn: 214942
* R600/SI: Do abs/neg folding with ComplexPatternsTom Stellard2014-08-011-24/+30
| | | | | | | | | | Abs/neg folding has moved out of foldOperands and into the instruction selection phase using complex patterns. As a consequence of this change, we now prefer to select the 64-bit encoding for most instructions and the modifier operands have been dropped from integer VOP3 instructions. llvm-svn: 214467
* R600/SI: Simplify and fix handling of VOP2 in SIInstrInfo::legalizeOperandsTom Stellard2014-08-011-28/+48
| | | | | | | | | | | | We were incorrectly assuming that all VOP2 instructions can read SGPRs in Src0, but this is not true for instructions that read carry-in from VCC. The old logic has been replaced with new logic which checks the defined register classes of the VOP2 instruction to determine whether or not to legalize the operands. llvm-svn: 214465
* R600/SI: Fold immediates when shrinking instructionsTom Stellard2014-08-011-1/+1
| | | | | | | This will prevent us from using extra MOV instructions once we prefer selecting 64-bit instructions. llvm-svn: 214464
* R600/SI: Fix incorrect commute operation in shrink instructions passTom Stellard2014-08-011-0/+4
| | | | | | | | We were commuting the instruction by still shrinking it using the original opcode. NOTE: This is a candidate for the 3.5 branch. llvm-svn: 214463
* R600/SI: Consider adjacent offsets in getLdStBaseRegImmOfsMatt Arsenault2014-07-301-13/+39
| | | | | | | | | We can treat ds_read2_* as a single offset if the offsets are adjacent. No test since emission of read2 instructions for partially aligned loads isn't implemented yet. llvm-svn: 214269
* R600/SI: Implement getLdStBaseRegImmOfsMatt Arsenault2014-07-291-0/+58
| | | | llvm-svn: 214225
* R600/SI: Add isMUBUF / isMTBUFMatt Arsenault2014-07-291-0/+8
| | | | | | Also add missing comments about how the flags work. llvm-svn: 214195
* Fix typos / grammar.Matt Arsenault2014-07-291-1/+1
| | | | llvm-svn: 214147
* R600/SI: Fix return type for isMIMG / isSMRDMatt Arsenault2014-07-281-2/+2
| | | | | | All the others use bool, so these should too. llvm-svn: 214106
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