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* R600/SI: Add instruction shrinking passTom Stellard2014-07-211-0/+9
| | | | | | This pass converts 64-bit instructions to 32-bit when possible. llvm-svn: 213561
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-211-1/+20
| | | | llvm-svn: 213551
* R600/SI: Store constant initializer data in constant memoryTom Stellard2014-07-211-0/+20
| | | | | | | | | | | | This implements a solution for constant initializers suggested by Vadim Girlin, where we store the data after the shader code and then use the S_GETPC instruction to compute its address. This saves use the trouble of creating a new buffer for constant data and then having to pass the pointer to the kernel via user SGPRs or the input buffer. llvm-svn: 213530
* R600/SI: Add verifier check for immediates in register operands.Tom Stellard2014-07-021-1/+8
| | | | llvm-svn: 212214
* R600/SI: Verify restrictions on div_scale operands.Matt Arsenault2014-06-231-0/+35
| | | | llvm-svn: 211524
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-181-0/+1
| | | | llvm-svn: 211187
* R600/SI: Match cttz_zero_undefMatt Arsenault2014-06-171-0/+1
| | | | llvm-svn: 211116
* R600/SI: Match ctlz_zero_undefMatt Arsenault2014-06-171-0/+1
| | | | llvm-svn: 211115
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-3/+3
| | | | llvm-svn: 210869
* R600/SI: Emit an error when attempting to spill VGPRs v4Tom Stellard2014-06-101-10/+24
| | | | | | | | | | | | | | | | | | I can't get VGPR spilling to work reliable, so for now just emit an error when the register allocator tries to spill VGPRs. v2: - Fix build v3: - Added crash fix when spilling SPGRs v4: - Use V_MOV_B32 as a dummy instruction instead of S_NOP Patch by: Darren Powell https://bugs.freedesktop.org/show_bug.cgi?id=75276 llvm-svn: 210588
* R600/SI: Fix a crash when spilling SGPRsTom Stellard2014-06-101-11/+7
| | | | | | | | | | | We need to make sure only one new instruction is added when spilling otherwise the register allocator may crash. This fixes a crash in the game Antichamber. https://bugs.freedesktop.org/show_bug.cgi?id=75276 llvm-svn: 210587
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-101-0/+45
| | | | llvm-svn: 210568
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-101-0/+5
| | | | llvm-svn: 210567
* R600/SI: Keep 64-bit not on SALUMatt Arsenault2014-06-091-7/+61
| | | | llvm-svn: 210476
* Fix typosMatt Arsenault2014-06-031-2/+2
| | | | llvm-svn: 210135
* R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-05-151-0/+18
| | | | | | This prevents a future commit from regressing the load-i1.ll test. llvm-svn: 208887
* R600/SI: Try to fix BFE operands when moving to VALUMatt Arsenault2014-05-131-1/+1
| | | | | | This was broken by r208479 llvm-svn: 208740
* R600/SI: Prettier display of input modifiersVincent Lejeune2014-05-101-4/+7
| | | | llvm-svn: 208479
* R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructionsTom Stellard2014-05-091-4/+35
| | | | llvm-svn: 208432
* R600/SI: Only create one instruction when spilling/restoring register v3Tom Stellard2014-05-021-25/+138
| | | | | | | | | | | | | | | | | | The register spiller assumes that only one new instruction is created when spilling and restoring registers, so we need to emit pseudo instructions for vector register spills and lower them after register allocation. v2: - Fix calculation of lane index - Extend VGPR liveness to end of program. v3: - Use SIMM16 field of S_NOP to specify multiple NOPs. https://bugs.freedesktop.org/show_bug.cgi?id=75005 llvm-svn: 207843
* R600/SI: Teach moveToVALU how to handle some SMRD instructionsTom Stellard2014-04-301-1/+47
| | | | llvm-svn: 207660
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-5/+5
| | | | llvm-svn: 207197
* R600/SI: Try to use scalar BFE.Matt Arsenault2014-04-181-0/+23
| | | | | | | | Use scalar BFE with constant shift and offset when possible. This is complicated by the fact that the scalar version packs the two operands of the vector version into one. llvm-svn: 206558
* R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16Matt Arsenault2014-04-181-14/+38
| | | | llvm-svn: 206547
* R600/SI: Teach SIInstrInfo::moveToVALU() how to handle PHI instructionsTom Stellard2014-04-171-3/+15
| | | | llvm-svn: 206498
* R600/SI: Legalize operands after changing dst reg in FixSGPRCopiesTom Stellard2014-04-171-2/+4
| | | | | | Otherwise we may not legalize some illegal REG_SEQUENCE instructions. llvm-svn: 206497
* R600/SI: Refactor SOPC classes slightly.Matt Arsenault2014-04-111-0/+6
| | | | | | | Better match what is done for VOPC to eventually prefer selecting these. llvm-svn: 206048
* R600/SI: Match not instruction.Matt Arsenault2014-04-091-0/+1
| | | | llvm-svn: 205837
* R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-04-071-0/+2
| | | | llvm-svn: 205732
* R600/SI: Implement shouldConvertConstantLoadToIntImmMatt Arsenault2014-03-311-18/+26
| | | | llvm-svn: 205244
* R600/SI: Implement SIInstrInfo::isTriviallyRematerializable()Tom Stellard2014-03-311-0/+12
| | | | llvm-svn: 205188
* R600/SI: Fix extra mov from legalizing 64-bit SALU ops.Matt Arsenault2014-03-241-14/+26
| | | | | | | Check the register class of each operand individually to avoid an extra copy to a vgpr. llvm-svn: 204662
* R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.Matt Arsenault2014-03-241-16/+37
| | | | | | | No longer asserts, but now you get moves loading legal immediates into the split 32-bit operations. llvm-svn: 204661
* R600/SI: Fix 64-bit bit ops that require the VALU.Matt Arsenault2014-03-241-0/+76
| | | | | | | | Try to match scalar and first like the other instructions. Expand 64-bit ands to a pair of 32-bit ands since that is not available on the VALU. llvm-svn: 204660
* R600/SI: Move splitting 64-bit immediates to separate function.Matt Arsenault2014-03-241-39/+53
| | | | llvm-svn: 204651
* R600/SI: Fix warning with gcc 4.8.2Tom Stellard2014-03-241-1/+1
| | | | llvm-svn: 204618
* R600/SI: Move instruction patterns to scalar versions.Matt Arsenault2014-03-211-0/+7
| | | | | | | Some of them also had the pattern on both, so this removes the duplication. llvm-svn: 204492
* R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()Tom Stellard2014-03-211-1/+135
| | | | llvm-svn: 204476
* R600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()Tom Stellard2014-03-211-2/+50
| | | | llvm-svn: 204475
* R600/SI: Fix implementation of isInlineConstant() used by the verifierTom Stellard2014-03-171-14/+25
| | | | | | | | The type of the immediates should not matter as long as the encoding is equivalent to the encoding of one of the legal inline constants. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 204056
* R600/SI: Add generic checks to SIInstrInfo::verifyInstruction()Tom Stellard2014-03-171-0/+41
| | | | | | | Added checks for number of operands and operand register classes. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 204054
* Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson2014-03-131-1/+1
| | | | | | | | | | operator* on the by-operand iterators to return a MachineOperand& rather than a MachineInstr&. At this point they almost behave like normal iterators! Again, this requires making some existing loops more verbose, but should pave the way for the big range-based for-loop cleanups in the future. llvm-svn: 203865
* Move trivial getter into header.Matt Arsenault2014-03-111-6/+1
| | | | llvm-svn: 203517
* R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are usedTom Stellard2014-02-101-0/+12
| | | | | | | | | | | DS instructions that access local memory can only uses addresses that are less than or equal to the value of M0. When M0 is uninitialized, then we experience undefined behavior. This patch also changes the behavior to emit S_WQM_B64 on pixel shaders no matter what kind of DS instruction is used. llvm-svn: 201097
* Allow MachineCSE to coalesce trivial subregister copies the same way that it ↵Andrew Trick2013-12-171-0/+2
| | | | | | | | | | | | | | | | | | | | coalesces normal copies. Without this, MachineCSE is powerless to handle redundant operations with truncated source operands. This required fixing the 2-addr pass to handle tied subregisters. It isn't clear what combinations of subregisters can legally be tied, but the simple case of truncated source operands is now safely handled: %vreg11<def> = COPY %vreg1:sub_32bit; GR32:%vreg11 GR64:%vreg1 %vreg12<def> = COPY %vreg2:sub_32bit; GR32:%vreg12 GR64:%vreg2 %vreg13<def,tied1> = ADD32rr %vreg11<tied0>, %vreg12<kill>, %EFLAGS<imp-def> Test case: cse-add-with-overflow.ll. This exposed an existing bug in PPCInstrInfo::commuteInstruction. Thanks to Rafael for the test case: PowerPC/crash.ll. llvm-svn: 197465
* R600/SI: Implement spilling of SGPRs v5Tom Stellard2013-11-271-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions. v2: - Fix encoding of Lane Mask - Use correct register flags, so we don't overwrite the low dword when restoring multi-dword registers. v3: - Register spilling seems to hang the GPU, so replace all shaders that need spilling with a dummy shader. v4: - Fix *LANE definitions - Change destination reg class for 32-bit SMRD instructions v5: - Remove small optimization that was crashing Serious Sam 3. https://bugs.freedesktop.org/show_bug.cgi?id=68224 https://bugs.freedesktop.org/show_bug.cgi?id=71285 NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195880
* R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-181-2/+2
| | | | | | | Moving into a VSrc doesn't always work, since it could be replaced with an SGPR later. llvm-svn: 195042
* R600/SI: Fix multiple SGPR reads when using VCC.Matt Arsenault2013-11-181-0/+18
| | | | | | | No other SGPR operands are allowed, so if VCC is used, move the other to a VGPR. llvm-svn: 195041
* R600/SI: Move patterns to match add / sub to scalar instructionsMatt Arsenault2013-11-181-0/+4
| | | | llvm-svn: 195034
* R600/SI: Fix extra defs of VCC / SCC.Matt Arsenault2013-11-181-4/+15
| | | | | | | When replacing scalar operations with vector, the wrong implicit output register was used. llvm-svn: 195033
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