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path: root/llvm/lib/Target/R600/SIInstrInfo.cpp
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* R600/SI: Add instruction shrinking passTom Stellard2014-07-211-0/+9
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-211-1/+20
* R600/SI: Store constant initializer data in constant memoryTom Stellard2014-07-211-0/+20
* R600/SI: Add verifier check for immediates in register operands.Tom Stellard2014-07-021-1/+8
* R600/SI: Verify restrictions on div_scale operands.Matt Arsenault2014-06-231-0/+35
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-181-0/+1
* R600/SI: Match cttz_zero_undefMatt Arsenault2014-06-171-0/+1
* R600/SI: Match ctlz_zero_undefMatt Arsenault2014-06-171-0/+1
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-3/+3
* R600/SI: Emit an error when attempting to spill VGPRs v4Tom Stellard2014-06-101-10/+24
* R600/SI: Fix a crash when spilling SGPRsTom Stellard2014-06-101-11/+7
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-101-0/+45
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-101-0/+5
* R600/SI: Keep 64-bit not on SALUMatt Arsenault2014-06-091-7/+61
* Fix typosMatt Arsenault2014-06-031-2/+2
* R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-05-151-0/+18
* R600/SI: Try to fix BFE operands when moving to VALUMatt Arsenault2014-05-131-1/+1
* R600/SI: Prettier display of input modifiersVincent Lejeune2014-05-101-4/+7
* R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructionsTom Stellard2014-05-091-4/+35
* R600/SI: Only create one instruction when spilling/restoring register v3Tom Stellard2014-05-021-25/+138
* R600/SI: Teach moveToVALU how to handle some SMRD instructionsTom Stellard2014-04-301-1/+47
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-5/+5
* R600/SI: Try to use scalar BFE.Matt Arsenault2014-04-181-0/+23
* R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16Matt Arsenault2014-04-181-14/+38
* R600/SI: Teach SIInstrInfo::moveToVALU() how to handle PHI instructionsTom Stellard2014-04-171-3/+15
* R600/SI: Legalize operands after changing dst reg in FixSGPRCopiesTom Stellard2014-04-171-2/+4
* R600/SI: Refactor SOPC classes slightly.Matt Arsenault2014-04-111-0/+6
* R600/SI: Match not instruction.Matt Arsenault2014-04-091-0/+1
* R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-04-071-0/+2
* R600/SI: Implement shouldConvertConstantLoadToIntImmMatt Arsenault2014-03-311-18/+26
* R600/SI: Implement SIInstrInfo::isTriviallyRematerializable()Tom Stellard2014-03-311-0/+12
* R600/SI: Fix extra mov from legalizing 64-bit SALU ops.Matt Arsenault2014-03-241-14/+26
* R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.Matt Arsenault2014-03-241-16/+37
* R600/SI: Fix 64-bit bit ops that require the VALU.Matt Arsenault2014-03-241-0/+76
* R600/SI: Move splitting 64-bit immediates to separate function.Matt Arsenault2014-03-241-39/+53
* R600/SI: Fix warning with gcc 4.8.2Tom Stellard2014-03-241-1/+1
* R600/SI: Move instruction patterns to scalar versions.Matt Arsenault2014-03-211-0/+7
* R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()Tom Stellard2014-03-211-1/+135
* R600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()Tom Stellard2014-03-211-2/+50
* R600/SI: Fix implementation of isInlineConstant() used by the verifierTom Stellard2014-03-171-14/+25
* R600/SI: Add generic checks to SIInstrInfo::verifyInstruction()Tom Stellard2014-03-171-0/+41
* Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson2014-03-131-1/+1
* Move trivial getter into header.Matt Arsenault2014-03-111-6/+1
* R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are usedTom Stellard2014-02-101-0/+12
* Allow MachineCSE to coalesce trivial subregister copies the same way that it ...Andrew Trick2013-12-171-0/+2
* R600/SI: Implement spilling of SGPRs v5Tom Stellard2013-11-271-0/+62
* R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-181-2/+2
* R600/SI: Fix multiple SGPR reads when using VCC.Matt Arsenault2013-11-181-0/+18
* R600/SI: Move patterns to match add / sub to scalar instructionsMatt Arsenault2013-11-181-0/+4
* R600/SI: Fix extra defs of VCC / SCC.Matt Arsenault2013-11-181-4/+15
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