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path: root/llvm/lib/Target/R600/R600RegisterInfo.cpp
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* R600 -> AMDGPU renameTom Stellard2015-06-131-91/+0
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-111-4/+6
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-131-10/+0
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-4/+3
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-151-0/+13
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-8/+8
* R600: Simplify handling of private address spaceTom Stellard2013-10-221-6/+1
* R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2Tom Stellard2013-08-141-10/+0
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-6/+5
* R600: Use bottom up scheduling algorithmVincent Lejeune2013-05-171-1/+5
* R600: Mark all members of the TRegMem register class as reservedTom Stellard2013-02-191-0/+6
* R600: Consolidate sub register indices.Tom Stellard2013-02-071-4/+4
* R600: Support for indirect addressing v4Tom Stellard2013-02-061-0/+14
* R600: improve inputs/interpolation handlingTom Stellard2013-02-051-6/+0
* R600: rework handling of the constantsTom Stellard2013-01-231-5/+1
* Add R600 backendTom Stellard2012-12-111-0/+89
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