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path: root/llvm/lib/Target/R600/R600MachineScheduler.cpp
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* R600 -> AMDGPU renameTom Stellard2015-06-131-469/+0
* Remove a few more calls to TargetMachine::getSubtarget from theEric Christopher2015-02-191-1/+1
* [PM] Remove the old 'PassManager.h' header file at the top level ofChandler Carruth2015-02-131-1/+1
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-301-3/+2
* Fix float division-by-zero in R600 scheduler.Alexey Samsonov2014-09-171-14/+18
* R600: Remove unused includeMatt Arsenault2014-08-041-1/+0
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-0/+1
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-5/+5
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
* Factor MI-Sched in preparation for post-ra scheduling support.Andrew Trick2013-12-281-4/+3
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-151-32/+0
* R600: Don't use trans slot for instructions that read LDS source registersTom Stellard2013-09-121-0/+4
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-041-12/+21
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-311-21/+12
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-311-12/+21
* R600: Support schedule and packetization of trans-only instVincent Lejeune2013-06-291-7/+18
* R600: Add local memory support via LDSTom Stellard2013-06-281-2/+10
* R600: Add support for GROUP_BARRIER instructionTom Stellard2013-06-281-1/+5
* R600: Use a refined heuristic to choose when switching clauseVincent Lejeune2013-06-071-9/+43
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-071-0/+1
* R600: Remove leftover code in R600MachineScheduler.cppVincent Lejeune2013-06-061-16/+0
* R600: Schedule copy from phys register at beginning of blockVincent Lejeune2013-06-051-1/+31
* R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard2013-06-051-2/+34
* Move passes from namespace llvm into anonymous namespaces. Sort includes whil...Benjamin Kramer2013-05-231-1/+1
* R600: Use bottom up scheduling algorithmVincent Lejeune2013-05-171-23/+28
* R600: Use depth first scheduling algorithmVincent Lejeune2013-05-171-52/+26
* R600: Replace big texture opcode switch in scheduler by usesTC/usesVCVincent Lejeune2013-05-171-23/+3
* R600: Relax some vector constraints on Dot4.Vincent Lejeune2013-05-171-2/+2
* R600: Factorize Fetch size limit inside AMDGPUSubTargetVincent Lejeune2013-05-171-8/+4
* R600: Factorize maximum alu per clause in a single locationVincent Lejeune2013-04-031-1/+1
* R600: Factorize code handling Const Read Port limitationVincent Lejeune2013-03-141-68/+7
* R600MachineScheduler.cpp: Fix use cases of dbgs(). Don't include <iostream> h...NAKAMURA Takumi2013-03-111-1/+2
* R600: initial scheduler codeVincent Lejeune2013-03-051-0/+487
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