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path: root/llvm/lib/Target/R600/AMDGPURegisterInfo.cpp
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* R600 -> AMDGPU renameTom Stellard2015-06-131-63/+0
| | | | llvm-svn: 239657
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-111-4/+1
| | | | | | classes. llvm-svn: 231954
* R600/SI: Enable inline assemblyTom Stellard2014-12-031-2/+1
| | | | | | | | We just needed to remove the assertion in AMDGPURegisterInfo::getFrameRegister(), which is called when initializing the parser for inline assembly. llvm-svn: 223197
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-2/+2
| | | | llvm-svn: 210869
* Use range forMatt Arsenault2014-05-151-1/+1
| | | | llvm-svn: 208922
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-041-3/+3
| | | | llvm-svn: 205610
* Use llvm_unreachable instead of assert(0)Matt Arsenault2013-12-101-1/+1
| | | | llvm-svn: 196971
* R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2Tom Stellard2013-08-141-19/+13
| | | | | | | | | | | | Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG instructions should make it easier for the register allocator to coalasce unnecessary copies. v2: - Use an SGPR register class if all the operands of BUILD_VECTOR are SGPRs. llvm-svn: 188427
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-4/+2
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183561
* R600: Consolidate sub register indices.Tom Stellard2013-02-071-16/+16
| | | | | | | | | | Use sub0-15 everywhere. Patch by: Michel Dänzerr Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 174610
* R600: Support for indirect addressing v4Tom Stellard2013-02-061-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* Update AMDGPURegisterInfo::eliminateFrameIndex() corresponding to r174083.NAKAMURA Takumi2013-01-311-0/+1
| | | | llvm-svn: 174106
* Add R600 backendTom Stellard2012-12-111-0/+51
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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