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path: root/llvm/lib/Target/R600/AMDGPUInstructions.td
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* R600 -> AMDGPU renameTom Stellard2015-06-131-682/+0
* R600/SI: Remove explicit m0 operand from DS instructionsTom Stellard2015-05-121-15/+22
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-281-1/+1
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-1/+1
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-1/+1
* Reduce dyn_cast<> to isa<> or cast<> where possible.Benjamin Kramer2015-04-101-2/+2
* R600/SI: Select V_BFE_U32 for and+shift with a non-literal offsetMarek Olsak2015-03-241-12/+10
* R600: Use new fmad node.Matt Arsenault2015-02-201-5/+0
* R600/SI: Don't set isCodeGenOnly = 1 on all instructionsTom Stellard2015-02-181-2/+0
* R600/SI: Extend private extload pattern to include zext loadsTom Stellard2015-02-171-4/+6
* R600/SI: Implement correct f64 fdivMatt Arsenault2015-02-141-11/+4
* MathExtras: Bring Count(Trailing|Leading)Ones and CountPopulation in line wit...Benjamin Kramer2015-02-121-1/+1
* R600/SI: Only select cvt_flr/cvt_rpi with no NaNs.Matt Arsenault2015-01-311-2/+4
* R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32Matt Arsenault2015-01-151-0/+17
* R600/SI: Make more unordered comparisons legalMatt Arsenault2014-12-111-1/+1
* R600/SI: Use unordered not equal instructionsMatt Arsenault2014-12-111-4/+14
* R600/SI: Start implementing an assemblerTom Stellard2014-11-141-0/+2
* R600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGsMatt Arsenault2014-11-021-4/+5
* R600/SI: Add global atomicrmw xchgAaron Watry2014-10-171-0/+1
* R600/SI: Add global atomicrmw xorAaron Watry2014-10-171-0/+1
* R600/SI: Add global atomicrmw orAaron Watry2014-10-171-0/+1
* R600/SI: Add global atomicrmw min/uminAaron Watry2014-10-171-0/+2
* R600/SI: Add global atomicrmw max/umaxAaron Watry2014-10-171-0/+2
* R600/SI: Add global atomicrmw andAaron Watry2014-10-171-0/+1
* R600/SI: Add global atomicrmw subAaron Watry2014-10-171-0/+1
* R600/SI: Add support for global atomic addTom Stellard2014-09-251-0/+8
* Revert "R600/SI: Add support for global atomic add"Tom Stellard2014-09-221-8/+0
* R600/SI: Add support for global atomic addTom Stellard2014-09-221-0/+8
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-0/+46
* R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignmentTom Stellard2014-08-221-0/+11
* R600/SI: Fix build warningTom Stellard2014-08-011-1/+1
* R600/SI: Do abs/neg folding with ComplexPatternsTom Stellard2014-08-011-0/+8
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-211-0/+26
* R600: Add predicate for UnsafeFPMathMatt Arsenault2014-07-151-0/+1
* R600: Add denormal handling subtarget features.Matt Arsenault2014-07-141-0/+3
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-241-4/+11
* R600/SI: Add intrinsics for various math instructions.Matt Arsenault2014-06-191-0/+10
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-131-0/+20
* R600: Mostly remove remaining AMDIL intrinsics.Matt Arsenault2014-06-121-1/+1
* R600/SI: Add common 64-bit LDS atomicsMatt Arsenault2014-06-111-0/+8
* R600/SI: Add 32-bit LDS atomic cmpxchgMatt Arsenault2014-06-111-0/+9
* R600/SI: Refactor local atomics.Matt Arsenault2014-06-111-7/+17
* R600: Handle fcopysignMatt Arsenault2014-06-101-1/+14
* R600/SI: Fix [s|u]int_to_fp for i1Matt Arsenault2014-05-311-0/+2
* R600: Expand mul24 for GPUs without itMatt Arsenault2014-05-221-8/+21
* R600: Expand mad24 for GPUs without itMatt Arsenault2014-05-221-0/+10
* R600: Add intrinsics for mad24Matt Arsenault2014-05-221-0/+11
* R600/SI: Print more immediates in hex formatMatt Arsenault2014-04-151-0/+12
* R600: Match 24-bit arithmetic patterns in a Target DAGCombineTom Stellard2014-04-071-3/+0
* R600: Reorganize tablegen instruction definitionsTom Stellard2014-03-241-0/+3
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