summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
Commit message (Expand)AuthorAgeFilesLines
...
* R600: Implement ComputeNumSignBitsForTargetNode for BFEMatt Arsenault2014-05-221-0/+25
* R600: Implement computeMaskedBitsForTargetNode for BFEMatt Arsenault2014-05-221-1/+29
* R600: Add intrinsics for mad24Matt Arsenault2014-05-221-0/+10
* R600: Add comment describing problems with LowerConstantInitializerMatt Arsenault2014-05-211-0/+10
* R600: Partially fix constant initializers for structs and vectors.Matt Arsenault2014-05-211-6/+33
* Use cast<> instead of unchecked dyn_castMatt Arsenault2014-05-211-1/+1
* Use range forMatt Arsenault2014-05-151-6/+2
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-141-14/+14
* R600: Add mul24 intrinsicsMatt Arsenault2014-05-121-0/+8
* Fix return before elseMatt Arsenault2014-05-111-18/+18
* R600: Expand i64 SELECT_CCTom Stellard2014-05-091-0/+2
* R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()Tom Stellard2014-05-091-9/+13
* R600: Promote f64 vector load/stores to i64 for consistencyMatt Arsenault2014-05-081-0/+6
* R600: Expand i64 ISD:SUBTom Stellard2014-05-051-0/+1
* R600: Expand vector sin and cos.Tom Stellard2014-05-021-0/+2
* R600: Expand TruncStore i64 -> {i16,i8}Tom Stellard2014-05-021-0/+2
* R600: optimize the UDIVREM 64 algorithmTom Stellard2014-04-291-22/+44
* R600: Implement iterative algorithm for udivremTom Stellard2014-04-291-0/+50
* R600: Change UDIV/UREM to UDIVREM when legalizing typesTom Stellard2014-04-291-1/+19
* R600: remove unused variableTom Stellard2014-04-291-2/+0
* Convert more SelectionDAG functions to use ArrayRef.Craig Topper2014-04-281-1/+1
* Convert SelectionDAG::getMergeValues to use ArrayRef.Craig Topper2014-04-271-1/+1
* Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.Craig Topper2014-04-261-10/+6
* R600: Fix function name printing in LowerCallMatt Arsenault2014-04-251-1/+3
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-1/+1
* R600: Emit error instead of unreachable on function callMatt Arsenault2014-04-221-0/+59
* R600: Change how vector truncating stores are packed.Matt Arsenault2014-04-221-11/+25
* R600: Make sign_extend_inreg legal.Matt Arsenault2014-04-221-70/+11
* R600: Add comment clariying use of sext for result of MUL_U24Tom Stellard2014-04-171-0/+2
* R600: Expand sign extension of vectors.Matt Arsenault2014-04-161-16/+0
* R600/SI: Fix loads of i1Matt Arsenault2014-04-151-0/+14
* Break PseudoSourceValue out of the Value hierarchy. It is now the root of its...Nick Lewycky2014-04-151-1/+2
* Move ExtractVectorElements to SelectionDAG.Matt Arsenault2014-04-111-20/+6
* R600: Match 24-bit arithmetic patterns in a Target DAGCombineTom Stellard2014-04-071-0/+84
* Use .data() instead of &x[0]Matt Arsenault2014-04-071-9/+10
* R600: Compute masked bits for min and maxMatt Arsenault2014-03-311-0/+44
* R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.Matt Arsenault2014-03-311-0/+24
* R600: Add target nodes for BFM and BFIMatt Arsenault2014-03-311-0/+2
* R600: Implement isZExtFree.Matt Arsenault2014-03-271-0/+16
* R600/SI: Fix unreachable with a sext_in_reg to an illegal type.Matt Arsenault2014-03-271-0/+18
* R600: Add a testcase for sext_in_reg I missed.Matt Arsenault2014-03-261-0/+2
* R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cppMatt Arsenault2014-03-251-0/+9
* R600: Implement isNarrowingProfitable.Matt Arsenault2014-03-241-0/+10
* R600: Match sign_extend_inreg to BFE instructionsMatt Arsenault2014-03-171-0/+111
* R600: Remove unnecessary attempt to zext a pointer.Matt Arsenault2014-03-151-3/+6
* R600: Code cleanup.Matt Arsenault2014-03-151-11/+12
* R600: Fix trunc store from i64 to i1Matt Arsenault2014-03-121-0/+6
* R600: Calculate store mask instead of using switch.Matt Arsenault2014-03-111-17/+3
* Use .data() instead of &x[0]Matt Arsenault2014-03-111-2/+2
* R600: Fix extloads from i8 / i16 to i64.Matt Arsenault2014-03-061-2/+14
OpenPOWER on IntegriCloud