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* R600 -> AMDGPU renameTom Stellard2015-06-131-1371/+0
| | | | llvm-svn: 239657
* R600/SI: Remove explicit m0 operand from DS instructionsTom Stellard2015-05-121-20/+59
| | | | | | | Instead add m0 as an implicit operand. This helps avoid spills of the m0 register in some cases. llvm-svn: 237141
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-281-93/+107
| | | | | | | | | | | | | | | | | | | | | | | | | [DebugInfo] Add debug locations to constant SD nodes This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235989
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-107/+93
| | | | | | | This breaks a test: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870 llvm-svn: 235987
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-93/+107
| | | | | | | | | | | | | | | | | | | | | | | This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235977
* Reduce dyn_cast<> to isa<> or cast<> where possible.Benjamin Kramer2015-04-101-1/+1
| | | | | | No functional change intended. llvm-svn: 234586
* R600/SI: Custom-select 32-bit S_BFE from bitwise opcodesMarek Olsak2015-03-241-12/+104
| | | | llvm-svn: 233078
* R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructionsTom Stellard2015-02-271-4/+7
| | | | llvm-svn: 230757
* R600/SI: Use complex operand folding for div_scaleMatt Arsenault2015-02-141-12/+7
| | | | llvm-svn: 229238
* R600/SI: Store immediate offsets > 12-bits in soffsetTom Stellard2015-02-111-13/+19
| | | | | | | This will save us from having to extend these offsets to 64-bits and storing them in a pair of vgprs. llvm-svn: 228776
* R600/SI: Add soffset operand to mubuf addr64 instructionTom Stellard2015-02-111-7/+8
| | | | | | We were previously hard-coding soffset to 0. llvm-svn: 228775
* R600: Don't promote i64 stores to v2i32 during DAG legalizationTom Stellard2015-02-041-0/+25
| | | | | | | We take care of this during instruction selection now. This fixes a potential infinite loop when lowering misaligned stores. llvm-svn: 228188
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-301-33/+29
| | | | | | without a Function argument. llvm-svn: 227638
* R600/SI: Move i64 -> v2i32 load promotion into AMDGPUDAGToDAGISel::Select()Tom Stellard2015-01-231-0/+22
| | | | | | | | | | | We used to do this promotion during DAG legalization, but this caused an infinite loop in ExpandUnalignedLoad() because it assumed that i64 loads were legal if i64 was a legal type. It also seems better to report i64 loads as legal, since they actually are and we were just promoting them to simplify our tablegen files. llvm-svn: 226945
* R600/SI: Use external symbols for scratch bufferTom Stellard2015-01-201-5/+16
| | | | | | | | We were passing the scratch buffer address to the shaders via user sgprs, but now we use external symbols and have the driver patch the shader using reloc information. llvm-svn: 226586
* R600/SI: Don't store scratch buffer frame index in MUBUF offset fieldTom Stellard2015-01-201-16/+0
| | | | | | | | We don't have a good way of legalizing this if the frame index offset is more than the 12-bits, which is size of MUBUF's offset field, so now we store the frame index in the vaddr field. llvm-svn: 226584
* R600/SI: Use RegisterOperands to specify which operands can accept immediatesTom Stellard2015-01-121-1/+3
| | | | | | | | | | | | There are some operands which can take either immediates or registers and we were previously using different register class to distinguish between operands that could take immediates and those that could not. This patch switches to using RegisterOperands which should simplify the backend by reducing the number of register classes and also make it easier to implement the assembler. llvm-svn: 225662
* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-1/+1
| | | | | | | | | | | Use VGPR_32 register class instead. These two register classes were identical and having separate classes was causing SIInstrInfo::isLegalOperands() to be overly conservative in some cases. This change is necessary to prevent future paches from missing a folding opportunity in fneg-fabs.ll. llvm-svn: 225382
* R600/SI: Add class intrinsicMatt Arsenault2015-01-061-0/+11
| | | | llvm-svn: 225305
* R600/SI: Set the ATC bit on all resource descriptors for the HSA runtimeTom Stellard2014-12-021-1/+3
| | | | llvm-svn: 223125
* R600/SI: Get rid of FCLAMP_SI pseudoMatt Arsenault2014-11-131-0/+12
| | | | | | | It's not necessary. Also use complex patterns to allow src modifier usage. llvm-svn: 221916
* R600/SI: Move all rsrc building functions to SIISelLoweringMatt Arsenault2014-11-051-50/+9
| | | | llvm-svn: 221383
* R600/SI: Remove SI_ADDR64_RSRCMatt Arsenault2014-11-051-7/+6
| | | | llvm-svn: 221382
* R600/SI: Remove SI_BUFFER_RSRC pseudoMatt Arsenault2014-10-171-6/+23
| | | | | | | Just use REG_SEQUENCE directly, so there are fewer instructions to need to deal with later. llvm-svn: 220056
* R600/SI: Fix bug where immediates were being used in DS addr operandsTom Stellard2014-10-151-1/+4
| | | | | | | | | | | | | | | | | | | The SelectDS1Addr1Offset complex pattern always tries to store constant lds pointers in the offset operand and store a zero value in the addr operand. Since the addr operand does not accept immediates, the zero value needs to first be copied to a register. This newly created zero value will not go through normal instruction selection, so we need to manually insert a V_MOV_B32_e32 in the complex pattern. This bug was hidden by the fact that if there was another zero value in the DAG that had not been selected yet, then the CSE done by the DAG would use the unselected node for the addr operand rather than the one that was just created. This would lead to the zero value being selected and the DAG automatically inserting a V_MOV_B32_e32 instruction. llvm-svn: 219848
* R600/SI: Also try to use 0 base for misaligned 8-byte DS loads.Matt Arsenault2014-10-151-0/+17
| | | | llvm-svn: 219823
* R600/SI: Use DS offsets for constant addressesMatt Arsenault2014-10-141-0/+12
| | | | | | | | Use 0 as the base address for a constant address, so if we have a constant address we can save moves and form read2/write2s. llvm-svn: 219698
* R600/SI: Legalize CopyToReg during instruction selectionTom Stellard2014-10-091-0/+7
| | | | | | | The instruction emitter will crash if it encounters a CopyToReg node with a non-register operand like FrameIndex. llvm-svn: 219428
* R600/SI: Update VOP3b to not include obsolete operandsMatt Arsenault2014-09-301-8/+9
| | | | | | abs / neg are now part of the srcN_modifiers operands llvm-svn: 218691
* R600/SI: Add support for global atomic addTom Stellard2014-09-251-0/+21
| | | | llvm-svn: 218457
* R600/SI: Enable selecting SALU inside branchesTom Stellard2014-09-241-18/+0
| | | | | | We can do this now that the FixSGPRLiveRanges pass is working. llvm-svn: 218353
* Revert "R600/SI: Add support for global atomic add"Tom Stellard2014-09-221-21/+0
| | | | | | | | | This reverts commit r218254. The global_atomics.ll test fails with asserts disabled. For some reason, the compiler fails to produce the atomic no return variants. llvm-svn: 218257
* R600/SI: Add support for global atomic addTom Stellard2014-09-221-0/+21
| | | | llvm-svn: 218254
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-1/+75
| | | | llvm-svn: 217777
* R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of 64-bit operationsTom Stellard2014-09-051-1/+1
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=83416 llvm-svn: 217248
* R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignmentTom Stellard2014-08-221-0/+27
| | | | llvm-svn: 216279
* R600/SI: Use a ComplexPattern for DS loads and storesTom Stellard2014-08-221-0/+38
| | | | llvm-svn: 216278
* R600/SI: Make sure SCRATCH_WAVE_OFFSET is added as Live-In to the functionTom Stellard2014-08-211-2/+7
| | | | | | This fixes a crash in an ocl conformance test. llvm-svn: 216219
* R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variantTom Stellard2014-08-111-49/+98
| | | | | | | This saves us from having to copy a 64-bit 0 value into VGPRs for BUFFER_* instruction which only have a 12-bit immediate offset. llvm-svn: 215399
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-2/+2
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-9/+13
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* R600/SI: Do abs/neg folding with ComplexPatternsTom Stellard2014-08-011-0/+35
| | | | | | | | | | Abs/neg folding has moved out of foldOperands and into the instruction selection phase using complex patterns. As a consequence of this change, we now prefer to select the 64-bit encoding for most instructions and the modifier operands have been dropped from integer VOP3 instructions. llvm-svn: 214467
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-211-2/+105
| | | | llvm-svn: 213551
* R600/SI: Use a ComplexPattern for MUBUF storesTom Stellard2014-06-241-0/+53
| | | | | | | | Now that non-leaf ComplexPatterns are allowed we can fold all the MUBUF store patterns into the instruction definition. We will also be able to reuse this new ComplexPattern for MUBUF loads and atomic operations. llvm-svn: 211644
* R600/SI: Fix div_scale intrinsic.Matt Arsenault2014-06-231-0/+28
| | | | | | | The operand that must match one of the others does matter, and implement selecting for it. llvm-svn: 211523
* R600/SI: Handle i64 sub.Matt Arsenault2014-06-231-12/+21
| | | | | | We can handle it the same way as add llvm-svn: 211514
* R600/SI: Move selection of i64 add to separate function.Matt Arsenault2014-06-231-39/+43
| | | | | | Also don't use a SmallVector for fixed size array. llvm-svn: 211513
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-171-1/+7
| | | | llvm-svn: 211110
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-0/+1
| | | | llvm-svn: 210869
* R600/SI: Fix selection failure on scalar_to_vectorMatt Arsenault2014-06-111-5/+21
| | | | | | | | | | | There seem to be only 2 places that produce these, and it's kind of tricky to hit them. Also fixes failure to bitcast between i64 and v2f32, although this for some reason wasn't actually broken in the simple bitcast testcase, but did in the scalar_to_vector one. llvm-svn: 210664
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