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* [PowerPC] Fix the assert of combineBVOfConsecutiveLoads when element num is 1QingShan Zhang2018-09-201-1/+2
* ScheduleDAG: Cleanup dumping code; NFCMatthias Braun2018-09-191-3/+2
* [PowerPC] Do not emit record-form rotates when record-form andi/andis sufficesNemanja Ivanovic2018-09-181-6/+28
* [PowerPC] Optimize compares fed by ANDISoNemanja Ivanovic2018-09-181-1/+2
* [PowerPC] Add Itineraries of IIC_IntMulHD for P7/P8QingShan Zhang2018-09-182-0/+8
* [PowerPC] Fix label address calculation for ppc64Strahinja Petrovic2018-09-171-1/+2
* [PowerPC] Fix the calling convention for i1 arguments on PPC32Lion Yang2018-09-141-5/+15
* Test commit: remove trailing whitespaceJosh Stone2018-09-111-1/+1
* [Target] Untangle disassemblersBenjamin Kramer2018-09-101-1/+1
* [PowerPC] Combine ADD to ADDZEQingShan Zhang2018-09-072-0/+98
* [PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8QingShan Zhang2018-09-032-0/+8
* [PPC] Remove Darwin support from POWER backend.Kit Barton2018-08-281-0/+3
* [PowerPC][MC] Support expressions in getMemRIX16Encoding.Sean Fertile2018-08-271-3/+9
* fix comment typoNico Weber2018-08-271-1/+1
* [PowerPC] Revert commit r339779Nemanja Ivanovic2018-08-274-9/+16
* [PowerPC] Recommit r340016 after fixing the reported issueNemanja Ivanovic2018-08-274-3/+38
* [PowerPC] Emit xscpsgndp instead of xxlor when copying floating point scalar ...Stefan Pintilie2018-08-241-1/+1
* Temporarily Revert "[PowerPC] Generate Power9 extswsli extend sign and shift ...Eric Christopher2018-08-214-38/+3
* [PowerPC] Add a peephole post RA to transform the inst that fed by addQingShan Zhang2018-08-202-50/+353
* [PowerPC] Generate lxsd instead of the ld->mtvsrd sequence for vector loadsStefan Pintilie2018-08-171-0/+29
* [PowerPC] Generate Power9 extswsli extend sign and shift immediate instructionNemanja Ivanovic2018-08-174-3/+38
* [MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth2018-08-161-24/+14
* [PowerPC] Enhance the selection(ISD::VSELECT) of vector typeNemanja Ivanovic2018-08-154-16/+9
* [PowerPC] Don't run BV DAG Combine before legalization if it assumes legal typesNemanja Ivanovic2018-08-151-3/+10
* [SDAG] Remove the reliance on MI's allocation strategy forChandler Carruth2018-08-141-6/+4
* [PowerPC] Improve codegen for vector loads using scalar_to_vectorZaara Syeda2018-08-083-20/+83
* [PowerPC] Do not round values prior to converting to integerNemanja Ivanovic2018-08-022-3/+105
* [DAGCombiner][TargetLowering] Pass a SmallVector instead of a std::vector to ...Craig Topper2018-07-302-3/+3
* [DAGCombiner][PowerPC][AArch64] Pass Created vector by reference to BuildSDIV...Craig Topper2018-07-302-6/+4
* Remove trailing spaceFangrui Song2018-07-3019-46/+46
* DAG: Add calling convention argument to calling convention funcsMatt Arsenault2018-07-283-1/+5
* [Power9] Code Cleanup - Remove needsAggressiveScheduling()Stefan Pintilie2018-07-191-27/+8
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-07-182-4/+4
* Fix build failures from r337347, found by clangJustin Hibbits2018-07-183-15/+6
* Introduce codegen for the Signal Processing EngineJustin Hibbits2018-07-1818-614/+1323
* Complete the SPE instruction set patternsJustin Hibbits2018-07-186-225/+562
* Add PowerPC e500(v2) core scheduler and directives.Justin Hibbits2018-07-187-220/+497
* [PowerPC] Materialize more constants with CR-field set in late peepholeNemanja Ivanovic2018-07-131-5/+28
* [Power9] Add remaining __flaot128 builtin support for FMA round to oddStefan Pintilie2018-07-111-3/+12
* [Power9] Add __float128 builtins for Rounding OperationsStefan Pintilie2018-07-092-0/+22
* [Power9] [LLVM] Add __float128 support for trunc to double round to oddStefan Pintilie2018-07-091-1/+4
* [Power9] Add __float128 builtins for Round To OddStefan Pintilie2018-07-091-6/+25
* [Power9] Add __float128 support for compare operationsStefan Pintilie2018-07-093-2/+75
* [Power9] Add __float128 library call for fremStefan Pintilie2018-07-061-0/+2
* [Power9] Add lib calls for float128 operations with no equivalent PPC instruc...Lei Huang2018-07-051-0/+19
* [Power9] Optimize codgen for conversions of int to float128Lei Huang2018-07-051-0/+17
* [Power9] Ensure float128 in non-homogenous aggregates are passed via VSX regLei Huang2018-07-054-0/+43
* [Power9]Legalize and emit code for quad-precision convert from single-precisionLei Huang2018-07-052-2/+10
* [Power9] Implement float128 parameter passing and return valuesLei Huang2018-07-052-5/+25
* [Power9]Legalize and emit code for round & convert quad-precision valuesLei Huang2018-07-043-3/+26
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