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| author | Lei Huang <lei@ca.ibm.com> | 2018-07-05 04:18:37 +0000 |
|---|---|---|
| committer | Lei Huang <lei@ca.ibm.com> | 2018-07-05 04:18:37 +0000 |
| commit | d17c39ccaac649f3089804e2d6dc8227b5a90d4a (patch) | |
| tree | 6785c9aeaa7689d942dd6bc8ff3633f3e3099dae /llvm/lib/Target/PowerPC | |
| parent | a26f3be4546ae8cd3dae4fe945a36dca67d53329 (diff) | |
| download | bcm5719-llvm-d17c39ccaac649f3089804e2d6dc8227b5a90d4a.tar.gz bcm5719-llvm-d17c39ccaac649f3089804e2d6dc8227b5a90d4a.zip | |
[Power9]Legalize and emit code for quad-precision convert from single-precision
Legalize and emit code for quad-precision floating point operation conversion of
single-precision value to quad-precision.
Differential Revision: https://reviews.llvm.org/D47569
llvm-svn: 336307
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrVSX.td | 9 |
2 files changed, 10 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index c494b98da45..705e1e07710 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -13741,6 +13741,9 @@ bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { bool PPCTargetLowering::isFPExtFree(EVT DestVT, EVT SrcVT) const { assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && "invalid fpext types"); + // Extending to float128 is not free. + if (DestVT == MVT::f128) + return false; return true; } diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 9b5421c7210..1aea324995e 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -2531,8 +2531,8 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { // Quad-Precision Floating-Point Conversion Instructions: // Convert DP -> QP - def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc, []>; - def : Pat<(f128 (fpextend f64:$src)), (f128 (XSCVDPQP $src))>; + def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc, + [(set f128:$vT, (fpextend f64:$vB))]>; // Round & Convert QP -> DP (dword[1] is set to zero) def XSCVQPDP : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>; @@ -3380,6 +3380,11 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { // Round & Convert QP -> DP/SP def : Pat<(f64 (fpround f128:$src)), (f64 (XSCVQPDP $src))>; def : Pat<(f32 (fpround f128:$src)), (f32 (XSRSP (XSCVQPDPO $src)))>; + + // Convert SP -> QP + def : Pat<(f128 (fpextend f32:$src)), + (f128 (XSCVDPQP (COPY_TO_REGCLASS $src, VFRC)))>; + } // end HasP9Vector, AddedComplexity let Predicates = [HasP9Vector] in { |
