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| author | QingShan Zhang <qshanz@cn.ibm.com> | 2018-09-20 03:09:15 +0000 |
|---|---|---|
| committer | QingShan Zhang <qshanz@cn.ibm.com> | 2018-09-20 03:09:15 +0000 |
| commit | cae9425a3c4a2af6a306c1aa5c8acfd27136f3fc (patch) | |
| tree | e3ff984758903c788149407e756635da04e7c8f1 /llvm/lib/Target/PowerPC | |
| parent | f45de47c59680c57939cdc55952afcebf2e90bfe (diff) | |
| download | bcm5719-llvm-cae9425a3c4a2af6a306c1aa5c8acfd27136f3fc.tar.gz bcm5719-llvm-cae9425a3c4a2af6a306c1aa5c8acfd27136f3fc.zip | |
[PowerPC] Fix the assert of combineBVOfConsecutiveLoads when element num is 1
Building a vector out of multiple loads can be converted to a load of the vector type if the loads are consecutive.
But the special condition is that the element number is 1, such as <1 x i128>. So just early exit to fix the assert.
Patch By: wuzish (Zixuan Wu)
Differential Revision: https://reviews.llvm.org/D52072
llvm-svn: 342611
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index dba69a160d4..1e51393dbfa 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -11901,7 +11901,8 @@ static SDValue combineBVOfConsecutiveLoads(SDNode *N, SelectionDAG &DAG) { IsRoundOfExtLoad = LD->getExtensionType() == ISD::EXTLOAD; } // Not a build vector of (possibly fp_rounded) loads. - if (!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD) + if ((!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD) || + N->getNumOperands() == 1) return SDValue(); for (int i = 1, e = N->getNumOperands(); i < e; ++i) { |
