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path: root/llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
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* Refactor PPC target to separate MC routines from Target routines.Evan Cheng2011-07-251-194/+0
| | | | llvm-svn: 135942
* Most MCCodeEmitter's don't meed MCContext.Evan Cheng2011-07-111-3/+1
| | | | llvm-svn: 134922
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-5/+6
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* MC: Move target specific fixup info descriptors to TargetAsmBackend instead ofDaniel Dunbar2010-12-161-20/+0
| | | | | | | the MCCodeEmitter, which seems like a better organization. - Also, cleaned up some magic constants while in the area. llvm-svn: 121953
* add copy of comment to the code that will survive the mcjit'izationChris Lattner2010-11-161-0/+2
| | | | llvm-svn: 119308
* relax an assertion a bit, allowing the GPR argument ofChris Lattner2010-11-161-1/+2
| | | | | | | | these instructions to be encoded with getMachineOpValue. This unbreaks ExecutionEngine/2003-01-04-ArgumentBug.ll when running on a G5 llvm-svn: 119307
* split out an encoder for memri operands, allowing a relocation to be ploppedChris Lattner2010-11-151-5/+24
| | | | | | | | | | | | | | | | into the immediate field. This allows us to encode stuff like this: lbz r3, lo16(__ZL4init)(r4) ; globalopt.cpp:5 ; encoding: [0x88,0x64,A,A] ; fixup A - offset: 0, value: lo16(__ZL4init), kind: fixup_ppc_lo16 stw r3, lo16(__ZL1s)(r5) ; globalopt.cpp:6 ; encoding: [0x90,0x65,A,A] ; fixup A - offset: 0, value: lo16(__ZL1s), kind: fixup_ppc_lo16 With this, we should have a completely function MCCodeEmitter for PPC, wewt. llvm-svn: 119134
* add support for encoding the lo14 forms used for a few PPC64 addressingChris Lattner2010-11-151-5/+10
| | | | | | | | | modes. For example, we now get: ld r3, lo16(_G)(r3) ; encoding: [0xe8,0x63,A,0bAAAAAA00] ; fixup A - offset: 0, value: lo16(_G), kind: fixup_ppc_lo14 llvm-svn: 119133
* implement the start of support for lo16 and ha16, allowing us to get stuff like:Chris Lattner2010-11-151-3/+43
| | | | | | | lis r4, ha16(__ZL4init) ; encoding: [0x3c,0x80,A,A] ; fixup A - offset: 0, value: ha16(__ZL4init), kind: fixup_ppc_ha16 llvm-svn: 119127
* add a fixup for conditional branches, giving us output like this:Chris Lattner2010-11-151-7/+5
| | | | | | | beq cr0, LBB0_4 ; encoding: [0x41,0x82,A,0bAAAAAA00] ; fixup A - offset: 0, value: LBB0_4, kind: fixup_ppc_brcond14 llvm-svn: 119126
* change direct branches to encode with the same encoding methodChris Lattner2010-11-151-5/+19
| | | | | | | | as direct calls. Change conditional branches to encode with their own method, simplifying the JIT encoder and making room for adding an mc fixup. llvm-svn: 119125
* split call operands out to their own encoding class, simplifyingChris Lattner2010-11-151-2/+18
| | | | | | | | | | code in the JIT. Use this to form the first fixup for the PPC backend, giving us stuff like this: bl L_foo$stub ; encoding: [0b010010AA,A,A,0bAAAAAA01] ; fixup A - offset: 0, value: L_foo$stub, kind: fixup_ppc_br24 llvm-svn: 119123
* add proper encoding for MTCRF instead of using a hack.Chris Lattner2010-11-151-3/+17
| | | | llvm-svn: 119121
* add basic encoding support for immediates and registers, allowing us Chris Lattner2010-11-151-0/+7
| | | | | | | | | | to encode all of these instructions correctly (for example): mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6] stw r0, 8(r1) ; encoding: [0x90,0x01,0x00,0x08] stwu r1, -64(r1) ; encoding: [0x94,0x21,0xff,0xc0] llvm-svn: 119118
* add a dummy entry to fix a build errorChris Lattner2010-11-151-2/+2
| | | | llvm-svn: 119117
* Implement a basic MCCodeEmitter for PPC. This doesn't handleChris Lattner2010-11-151-0/+99
fixups yet, and doesn't handle actually encoding operand values, but this is enough for llc -show-mc-encoding to show the base instruction encoding information, e.g.: mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6] stw r0, 8(r1) ; encoding: [0x90,0x00,0x00,0x00] stwu r1, -64(r1) ; encoding: [0x94,0x00,0x00,0x00] Ltmp0: lhz r4, 4(r3) ; encoding: [0xa0,0x00,0x00,0x00] cmplwi cr0, r4, 8 ; encoding: [0x28,0x00,0x00,0x00] beq cr0, LBB0_2 ; encoding: [0x40,0x00,0x00,0x00] llvm-svn: 119116
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