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author | Chris Lattner <sabre@nondot.org> | 2010-11-15 08:02:41 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2010-11-15 08:02:41 +0000 |
commit | 8f4444d0031fce48a303ff3cba369ded93901d32 (patch) | |
tree | bf40e3bb614cfe15ecbe7c2c42426b8b85069e2c /llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp | |
parent | 15e9d5ef8ad0b9011080beda6546d7f3ff1464d7 (diff) | |
download | bcm5719-llvm-8f4444d0031fce48a303ff3cba369ded93901d32.tar.gz bcm5719-llvm-8f4444d0031fce48a303ff3cba369ded93901d32.zip |
add support for encoding the lo14 forms used for a few PPC64 addressing
modes. For example, we now get:
ld r3, lo16(_G)(r3) ; encoding: [0xe8,0x63,A,0bAAAAAA00]
; fixup A - offset: 0, value: lo16(_G), kind: fixup_ppc_lo14
llvm-svn: 119133
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp index 644f46f21d8..66c0bb72a9c 100644 --- a/llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp @@ -66,8 +66,8 @@ public: SmallVectorImpl<MCFixup> &Fixups) const; unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups) const; - unsigned getLO14Encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl<MCFixup> &Fixups) const; + unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups) const; unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups) const; @@ -147,15 +147,20 @@ unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo, return 0; } -unsigned PPCMCCodeEmitter::getLO14Encoding(const MCInst &MI, unsigned OpNo, +unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups) const { + // Encode (imm, reg) as a memrix, which has the low 14-bits as the + // displacement and the next 5 bits as the register #. + unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14; + const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); + if (MO.isImm()) + return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits; // Add a fixup for the branch target. Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_lo14)); - return 0; + return RegBits; } |