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path: root/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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* Remove the `hasFnAttr' method from Function.Bill Wendling2012-09-261-1/+1
* Specify MachinePointerInfo as refering to the argument value and offset of theRoman Divacky2012-09-241-3/+5
* Small structs for PPC64 SVR4 must be passed right-justified in registers.Bill Schmidt2012-09-191-47/+128
* Fix the isLocalCall() by checking for linker weakness as well.Roman Divacky2012-09-181-1/+2
* Optimize local func calls to not emit nop for TOC restoration.Roman Divacky2012-09-181-2/+10
* Fix PR11985Michael Liao2012-09-121-2/+2
* PPCISelLowering.cpp: Fix r162725.NAKAMURA Takumi2012-08-301-1/+5
* PPCISelLowering.cpp: Whitespace.NAKAMURA Takumi2012-08-301-1/+1
* Add PPC Freescale e500mc and e5500 subtargets.Hal Finkel2012-08-281-0/+15
* Eliminate redundant CR moves on PPC32.Hal Finkel2012-08-281-8/+14
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-241-8/+7
* Lower constant pools and jump tables via TOC on PPC64/SVR4.Roman Divacky2012-08-241-0/+16
* Fix typo and grammar. By Adhemerval Zanella.Roman Divacky2012-08-161-1/+1
* Add readcyclecounter lowering on PPC64.Hal Finkel2012-08-041-1/+3
* Target option DisableJumpTables is a gross hack. Move it to TargetLowering in...Evan Cheng2012-07-021-10/+17
* Add support for the PPC isel instruction.Hal Finkel2012-06-221-5/+31
* Convert the PPC backend to use the new FMA infrastructure.Hal Finkel2012-06-221-2/+23
* Add support for generating reg+reg (indexed) pre-inc loads on PPC.Hal Finkel2012-06-201-7/+2
* Add support for generating reg+reg preinc stores on PPC.Hal Finkel2012-06-191-1/+9
* Enable ILP scheduling for all nodes by default on PPC.Hal Finkel2012-06-101-4/+6
* PPC32 uses R2 as the TLS register. Fix the copy and paste.Roman Divacky2012-06-051-3/+3
* Implement local-exec TLS on PowerPC.Roman Divacky2012-06-041-1/+26
* Enable generating PPC pre-increment (r+imm) instructions by default.Hal Finkel2012-06-041-5/+3
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-251-11/+19
* effectively back out my last change (r155190)Gabor Greif2012-04-201-2/+2
* fix obviously bogus (IMO) operand index of the load in assertsGabor Greif2012-04-201-3/+3
* Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change s...Craig Topper2012-04-201-19/+19
* zap tabsGabor Greif2012-04-191-7/+7
* Always compute all the bits in ComputeMaskedBits.Rafael Espindola2012-04-041-14/+3
* Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.Roman Divacky2012-04-021-1/+10
* Enable prefetch generation on PPC64.Hal Finkel2012-04-011-0/+3
* Set the default PPC node scheduling preference to ILP (for the embedded cores).Hal Finkel2012-04-011-0/+9
* Fix dynamic linking on PPC64.Hal Finkel2012-03-311-8/+15
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-1/+1
* Fix small-integer VAARG on SVR4 ABI PPC64.Hal Finkel2012-03-241-5/+17
* Reorder includes in Target backends to following coding standards. Remove som...Craig Topper2012-03-171-7/+7
* Convert more static tables of registers used by calling convention to uint16_...Craig Topper2012-03-111-4/+4
* Use uint16_t to store registers and opcode in static tables in the target spe...Craig Topper2012-03-111-12/+12
* Convert PowerPC to register mask operands.Roman Divacky2012-03-061-0/+6
* Re-commit r151623 with fix. Only issue special no-return calls if it's a dire...Evan Cheng2012-02-281-3/+4
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack pre...Daniel Dunbar2012-02-281-4/+3
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-281-3/+4
* Make all pointers to TargetRegisterClass const since they are all pointers to...Craig Topper2012-02-221-1/+1
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-2/+1
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-1/+0
* Remove a bunch of unused variable assignments.Benjamin Kramer2012-01-201-2/+1
* Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through Code...Benjamin Kramer2012-01-151-2/+1
* Remove VectorExtras. This unused helper was written for a type of API that is...Benjamin Kramer2012-01-071-1/+0
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-131-0/+6
* Teach SelectionDAG to match more calls to libm functions onto existing SDNode...Owen Anderson2011-12-081-0/+7
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