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| author | Hal Finkel <hfinkel@anl.gov> | 2012-06-20 15:43:03 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-06-20 15:43:03 +0000 |
| commit | ca542beffec5534538a76764166253348c25e054 (patch) | |
| tree | 567a033eb899c94f339e8f92366b845522ceeca7 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | 8a31138521a1e457a5b1ac399c40e2b32b4dd033 (diff) | |
| download | bcm5719-llvm-ca542beffec5534538a76764166253348c25e054.tar.gz bcm5719-llvm-ca542beffec5534538a76764166253348c25e054.zip | |
Add support for generating reg+reg (indexed) pre-inc loads on PPC.
llvm-svn: 158823
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 48feb98be9b..dc50d860a87 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1106,13 +1106,8 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, return false; if (SelectAddressRegReg(Ptr, Offset, Base, DAG)) { - if (isa<StoreSDNode>(N)) { - AM = ISD::PRE_INC; - return true; - } - - // FIXME: reg+reg preinc loads - return false; + AM = ISD::PRE_INC; + return true; } // LDU/STU use reg+imm*4, others use reg+imm. |
