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path: root/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
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* Support building non-PICNate Begeman2005-07-211-56/+86
* Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5.Nate Begeman2005-07-201-3/+18
* Integrate SelectFPExpr into SelectExpr. This gets PPC32 closer to beingNate Begeman2005-07-191-338/+242
* Change *EXTLOAD to use an VTSDNode operand instead of being an MVTSDNode.Chris Lattner2005-07-101-2/+2
* Change TRUNCSTORE to use a VTSDNode operand instead of being an MVTSTDNodeChris Lattner2005-07-101-1/+1
* Make several cleanups to Andrews varargs change:Chris Lattner2005-07-051-19/+17
* Fix PowerPC varargsChris Lattner2005-07-051-24/+25
* Varargs is apparently currently broken on PPC. This hacks it so that itChris Lattner2005-07-011-4/+9
* Commit fix for generating conditional branch pseudo instructions thatNate Begeman2005-06-151-3/+8
* Commit a small improvement that is already in the x86 and ia64 backends toNate Begeman2005-06-141-0/+5
* Handle some more real world cases of rlwimi. These don't come up thatNate Begeman2005-06-081-10/+42
* Fix andrews changes to fit in 80 columnsChris Lattner2005-05-151-9/+18
* treat TAILCALL nodes identically to CALL nodesChris Lattner2005-05-131-1/+4
* Add an isTailCall flag to LowerCallToChris Lattner2005-05-131-2/+3
* Realize that we don't support fmod directly, fixing CodeGen/Generic/print-ari...Chris Lattner2005-05-131-1/+3
* rename the ADJCALLSTACKDOWN/ADJCALLSTACKUP nodes to be CALLSEQ_START/BEGIN.Chris Lattner2005-05-121-6/+6
* Pass in Calling Convention to use into LowerCallToChris Lattner2005-05-121-1/+2
* These targets don't like setccChris Lattner2005-05-121-0/+3
* Necessary changes to codegen cttz efficiently on PowerPCNate Begeman2005-05-111-6/+28
* fold and (shl X, C1), C2 -> rlwinm when possible. Many other cases are possi...Chris Lattner2005-05-091-1/+20
* fix typoAndrew Lenharth2005-05-041-1/+1
* Implement count leading zeros (ctlz), count trailing zeros (cttz), and countAndrew Lenharth2005-05-031-0/+5
* This target doesn't support the FSIN/FCOS/FSQRT nodes yetChris Lattner2005-04-301-0/+8
* Implement Value* tracking for loads and stores in the selection DAG. This en...Andrew Lenharth2005-04-271-11/+11
* Convert tabs to spacesMisha Brukman2005-04-221-3/+4
* Remove trailing whitespaceMisha Brukman2005-04-211-135/+135
* Match another form of eqvChris Lattner2005-04-211-1/+6
* Next round of PPC CR optimizations. For the following code:Nate Begeman2005-04-181-62/+95
* Change codegen for setcc to read the bit directly out of the conditionNate Begeman2005-04-181-42/+31
* Make pattern isel default for ppcNate Begeman2005-04-151-3/+2
* Implement multi-way branches through logical ops on condition registers.Nate Begeman2005-04-141-2/+68
* Start allocating condition registers. Almost all explicit uses of CR0 areNate Begeman2005-04-131-23/+26
* Implement the fold shift X, zext(Y) -> shift X, Y at the target level,Nate Begeman2005-04-131-6/+22
* Disbale the broken fold of shift + sz[ext] for nowNate Begeman2005-04-131-19/+0
* remove one more occurance of this that snuck inChris Lattner2005-04-131-1/+1
* Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emitChris Lattner2005-04-131-13/+0
* Fold shift by size larger than type size to undefNate Begeman2005-04-121-1/+0
* Implement setcc op, -1 sequencesNate Begeman2005-04-121-22/+41
* Implement bitfield clearsNate Begeman2005-04-121-11/+31
* Add recording variants of ISD::AND and ISD::OR. This kills almost 1000Nate Begeman2005-04-111-10/+43
* Fix another fixme: factor out the constant fp generation code.Nate Begeman2005-04-101-17/+2
* Fix 64 bit argument loading that straddles the args in regs / args on stackNate Begeman2005-04-101-7/+15
* Make sure that BRCOND branches can be converted into long branches too.Nate Begeman2005-04-101-1/+3
* Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.Nate Begeman2005-04-101-1/+2
* fix ISD::BRCONDTWOWAY codegen to not deference the end() iteratorNate Begeman2005-04-091-1/+1
* do not set the root to null if an argument is deadChris Lattner2005-04-091-1/+2
* Add rlwnm instruction for variable rotateNate Begeman2005-04-091-28/+76
* Optimize FSEL a bit for fneg arguments. This fixes the recently added testNate Begeman2005-04-091-11/+12
* This target does not yet support ISD::BRCONDTWOWAYChris Lattner2005-04-091-0/+1
* 64b: Expand S/UREMNate Begeman2005-04-091-7/+27
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