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| author | Chris Lattner <sabre@nondot.org> | 2005-07-10 01:56:13 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-07-10 01:56:13 +0000 |
| commit | 53676dfd33a98cbbb6abba62b044dccc90df5529 (patch) | |
| tree | 8dec792023602b8ab7837414931db20664c74645 /llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp | |
| parent | de0a4b198764c87de4dacce87950b899c40f7f5d (diff) | |
| download | bcm5719-llvm-53676dfd33a98cbbb6abba62b044dccc90df5529.tar.gz bcm5719-llvm-53676dfd33a98cbbb6abba62b044dccc90df5529.zip | |
Change *EXTLOAD to use an VTSDNode operand instead of being an MVTSDNode.
This is the last MVTSDNode.
This allows us to eliminate a bunch of special case code for handling
MVTSDNodes.
Also, remove some uses of dyn_cast that should really be cast (which is
cheaper in a release build).
llvm-svn: 22368
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp index f5a09a7f60f..5388eebb6bc 100644 --- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp +++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp @@ -1690,7 +1690,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { case ISD::ZEXTLOAD: case ISD::SEXTLOAD: { MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ? - Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType(); + Node->getValueType(0) : cast<VTSDNode>(Node->getOperand(3))->getVT(); bool sext = (ISD::SEXTLOAD == opcode); // Make sure we generate both values. @@ -1828,7 +1828,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { case ISD::SIGN_EXTEND: case ISD::SIGN_EXTEND_INREG: Tmp1 = SelectExpr(N.getOperand(0)); - switch(cast<MVTSDNode>(Node)->getExtraValueType()) { + switch(cast<VTSDNode>(Node->getOperand(1))->getVT()) { default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break; case MVT::i16: BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1); |

