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* [mips] Print BEQZL and BNEZL pseudo instructionsSimon Atanasyan2019-07-151-4/+4
| | | | | | One of the reasons - to be compatible with GNU tools. llvm-svn: 366133
* [mips] Remove "else-after-return". NFCSimon Atanasyan2019-07-151-1/+1
| | | | llvm-svn: 366064
* Delete dead storesFangrui Song2019-07-121-2/+1
| | | | llvm-svn: 365903
* [mips] Fix JmpLink to texternalsym and tglobaladdr on mcroMIPS R6Simon Atanasyan2019-07-122-1/+14
| | | | | | | | | | | | | | | | There is not match for the `MipsJmpLink texternalsym` and `MipsJmpLink tglobaladdr` patterns for microMIPS R6. As a result LLVM incorrectly selects the `JALRC16` compact 2-byte instruction which takes a target instruction address from a register only and assign `R_MIPS_32` relocation for this instruction. This relocation completely overwrites `JALRC16` and nearby instructions. This patch adds missed matching patterns, selects `BALC` instruction and assign a correct `R_MICROMIPS_PC26_S1` relocation. Differential Revision: https://reviews.llvm.org/D64552 llvm-svn: 365870
* [MIPS GlobalISel] Skip copies in addUseDef and addDefUsesPetar Avramovic2019-07-112-11/+48
| | | | | | | | | | | | Skip copies between virtual registers during search for UseDefs and DefUses. Since each operand has one def search for UseDefs is straightforward. But since operand can have many uses, we have to check all uses of each copy we traverse during search for DefUses. Differential Revision: https://reviews.llvm.org/D64486 llvm-svn: 365744
* [MIPS GlobalISel] RegBankSelect for chains of ambiguous instructionsPetar Avramovic2019-07-112-14/+77
| | | | | | | | | | | | | | | | | | | | When one of the uses/defs of ambiguous instruction is also ambiguous visit it recursively and search its uses/defs for instruction with only one mapping available. When all instruction in a chain are ambiguous arbitrary mapping can be selected. For s64 operands in ambiguous chain fprb is selected since it results in less instructions then having to narrow scalar s64 to s32. For s32 both gprb and fprb result in same number of instructions and gprb is selected like a general purpose option. At the moment we always avoid cross register bank copies. TODO: Implement a model for costs calculations of different mappings on same instruction and cross bank copies. Allow cross bank copies when appropriate according to cost model. Differential Revision: https://reviews.llvm.org/D64485 llvm-svn: 365743
* [MIPS GlobalISel] Select float and double phiPetar Avramovic2019-07-101-4/+25
| | | | | | | | Select float and double phi for MIPS32. Differential Revision: https://reviews.llvm.org/D64420 llvm-svn: 365627
* [MIPS GlobalISel] Select float and double load and storePetar Avramovic2019-07-101-22/+44
| | | | | | | | Select float and double load and store for MIPS32. Differential Revision: https://reviews.llvm.org/D64419 llvm-svn: 365626
* [mips] Show error in case of using FP64 mode on pre MIPS32R2 CPUSimon Atanasyan2019-07-091-0/+5
| | | | llvm-svn: 365508
* [MIPS GlobalISel] Register bank select for G_PHI. Select i64 phiPetar Avramovic2019-07-092-4/+35
| | | | | | | | | | | | | | | Select gprb or fprb when def/use register operand of G_PHI is used/defined by either: copy to/from physical register or instruction with only one mapping available for that use/def operand. Integer s64 phi is handled with narrowScalar when mapping is applied, produced artifacts are combined away. Manually set gprb to all register operands of instructions created during narrowScalar. Differential Revision: https://reviews.llvm.org/D64351 llvm-svn: 365494
* [MIPS GlobalISel] Regbanks for G_SELECT. Select i64, f32 and f64 selectPetar Avramovic2019-07-092-9/+35
| | | | | | | | | | | | | | | | | | Select gprb or fprb when def/use register operand of G_SELECT is used/defined by either: copy to/from physical register or instruction with only one mapping available for that use/def operand. Integer s64 select is handled with narrowScalar when mapping is applied, produced artifacts are combined away. Manually set gprb to all register operands of instructions created during narrowScalar. For selection of floating point s32 or s64 select it is enough to set fprb of appropriate size and selectImpl will do the rest. Differential Revision: https://reviews.llvm.org/D64350 llvm-svn: 365492
* [mips] Implement sge/sgeu pseudo instructionsSimon Atanasyan2019-07-093-0/+147
| | | | | | | | | | The `sge/sgeu Dst, Src1, Src2/Imm` pseudo instructions set register `Dst` to 1 if register `Src1` is greater than or equal `Src2/Imm` and to 0 otherwise. Differential Revision: https://reviews.llvm.org/D64314 llvm-svn: 365476
* [mips] Implement sgt/sgtu pseudo instructions with immediate operandSimon Atanasyan2019-07-093-0/+86
| | | | | | | | | The `sgt/sgtu Dst, Src1, Src2/Imm` pseudo instructions set register `Dst` to 1 if register `Src1` is greater than `Src2/Imm` and to 0 otherwise. Differential Revision: https://reviews.llvm.org/D64313 llvm-svn: 365475
* GlobalISel: Convert some build functions to using SrcOp/DstOpMatt Arsenault2019-07-081-2/+2
| | | | llvm-svn: 365343
* [MIPS GlobalISel] Register bank select for G_LOAD. Select i64 loadPetar Avramovic2019-07-083-10/+100
| | | | | | | | | | | | | | Select gprb or fprb when loaded value is used by either: copy to physical register or instruction with only one mapping available for that use operand. Load of integer s64 is handled with narrowScalar when mapping is applied, produced artifacts are combined away. Manually set gprb to all register operands of instructions created during narrowScalar. Differential Revision: https://reviews.llvm.org/D64269 llvm-svn: 365323
* [MIPS GlobalISel] Register bank select for G_STORE. Select i64 storePetar Avramovic2019-07-083-5/+344
| | | | | | | | | | | | | | Select gprb or fprb when stored value is defined by either: copy from physical register or instruction with only one mapping available for that def operand. Store of integer s64 is handled with narrowScalar when mapping is applied, produced artifacts are combined away. Manually set gprb to all register operands of instructions created during narrowScalar. Differential Revision: https://reviews.llvm.org/D64268 llvm-svn: 365322
* [mips] Refactor expandSeq and expandSeqI methods. NFCSimon Atanasyan2019-07-041-41/+43
| | | | llvm-svn: 365161
* [mips] Mark general scheduling model as completeSimon Atanasyan2019-07-031-2/+2
| | | | llvm-svn: 365034
* [mips] Add missing atomic instructions to general scheduling definitionsSimon Atanasyan2019-07-031-0/+16
| | | | llvm-svn: 365033
* [mips] Add missing microMIPS instructions to general scheduling definitionsSimon Atanasyan2019-07-031-12/+25
| | | | llvm-svn: 365032
* [mips] Add SIGRIE,GINVI,GINVT to general scheduling definitionsSimon Atanasyan2019-07-031-2/+5
| | | | llvm-svn: 365023
* [mips] Add missing mips16 instructions to general scheduling definitionsSimon Atanasyan2019-07-032-5/+6
| | | | llvm-svn: 365022
* [mips] Add missing MSA and ASE instructions to general scheduling definitionsSimon Atanasyan2019-07-031-0/+33
| | | | llvm-svn: 365021
* [mips] Replace some itineraries by instructions in the general scheduling ↵Simon Atanasyan2019-07-031-187/+668
| | | | | | definitions llvm-svn: 365020
* [mips] Mark P5600 scheduling model as completeSimon Atanasyan2019-07-021-1/+1
| | | | llvm-svn: 364902
* [mips] Add missing schedinfo for FPU load/store/conv instructionsSimon Atanasyan2019-07-021-4/+10
| | | | llvm-svn: 364900
* [mips] Map SNOP, NOP to the P5600Nop scheduler resourceSimon Atanasyan2019-07-021-2/+8
| | | | llvm-svn: 364899
* [mips] Add missing schedinfo for MIPSeh_return[32|64] instructionsSimon Atanasyan2019-07-011-1/+1
| | | | llvm-svn: 364850
* [mips] Add virtualization ASE to P5600 scheduling definitionsSimon Atanasyan2019-07-011-0/+5
| | | | llvm-svn: 364849
* [mips] Add missing schedinfo for LONG_BRANCH_* instructionsSimon Atanasyan2019-07-012-11/+27
| | | | llvm-svn: 364848
* [mips] Add missing schedinfo for MSA and ASE instructionsSimon Atanasyan2019-07-013-2/+12
| | | | llvm-svn: 364757
* [mips] Add missing schedinfo for atomic instructionsSimon Atanasyan2019-07-012-3/+22
| | | | llvm-svn: 364756
* [mips] Add missing schedinfo for ADJCALLSTACKDOWN, ADJCALLSTACKUPSimon Atanasyan2019-07-011-1/+1
| | | | llvm-svn: 364755
* [mips] Mark pseudo select instructions by the `hasNoSchedulingInfo` tagSimon Atanasyan2019-06-271-2/+2
| | | | llvm-svn: 364540
* [mips] Add new items to the list of features unsupported by P5600Simon Atanasyan2019-06-271-3/+3
| | | | llvm-svn: 364539
* [mips] Add GPR_64 predicate to some mov[zn] instructionsSimon Atanasyan2019-06-271-8/+10
| | | | llvm-svn: 364527
* [mips] Fix indentation and split long lines. NFCSimon Atanasyan2019-06-271-5/+5
| | | | llvm-svn: 364526
* [mips] Reformat MSA instruction definitions. NFCSimon Atanasyan2019-06-271-46/+32
| | | | llvm-svn: 364525
* [GlobalISel] Accept multiple vregs for lowerCall's resultDiana Picus2019-06-271-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Change the interface of CallLowering::lowerCall to accept several virtual registers for the call result, instead of just one. This is a follow-up to D46018. CallLowering::lowerReturn was similarly refactored in D49660 and lowerFormalArguments in D63549. With this change, we no longer pack the virtual registers generated for aggregates into one big lump before delegating to the target. Therefore, the target can decide itself whether it wants to handle them as separate pieces or use one big register. ARM and AArch64 have been updated to use the passed in virtual registers directly, which means we no longer need to generate so many merge/extract instructions. NFCI for AMDGPU, Mips and X86. Differential Revision: https://reviews.llvm.org/D63550 llvm-svn: 364511
* [GlobalISel] Accept multiple vregs in lowerFormalArgsDiana Picus2019-06-272-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the interface of CallLowering::lowerFormalArguments to accept several virtual registers for each formal argument, instead of just one. This is a follow-up to D46018. CallLowering::lowerReturn was similarly refactored in D49660. lowerCall will be refactored in the same way in follow-up patches. With this change, we forward the virtual registers generated for aggregates to CallLowering. Therefore, the target can decide itself whether it wants to handle them as separate pieces or use one big register. We also copy the pack/unpackRegs helpers to CallLowering to facilitate this. ARM and AArch64 have been updated to use the passed in virtual registers directly, which means we no longer need to generate so many merge/extract instructions. AArch64 seems to have had a bug when lowering e.g. [1 x i8*], which was put into a s64 instead of a p0. Added a test-case which illustrates the problem more clearly (it crashes without this patch) and fixed the existing test-case to expect p0. AMDGPU has been updated to unpack into the virtual registers for kernels. I think the other code paths fall back for aggregates, so this should be NFC. Mips doesn't support aggregates yet, so it's also NFC. x86 seems to have code for dealing with aggregates, but I couldn't find the tests for it, so I just added a fallback to DAGISel if we get more than one virtual register for an argument. Differential Revision: https://reviews.llvm.org/D63549 llvm-svn: 364510
* [GlobalISel] Allow multiple VRegs in ArgInfo. NFCDiana Picus2019-06-271-5/+9
| | | | | | | | | | | Allow CallLowering::ArgInfo to contain more than one virtual register. This is useful when passes split aggregates into several virtual registers, but need to also provide information about the original type to the call lowering. Used in follow-up patches. Differential Revision: https://reviews.llvm.org/D63548 llvm-svn: 364509
* GlobalISel: Remove unsigned variant of SrcOpMatt Arsenault2019-06-245-40/+41
| | | | | | | | | Force using Register. One downside is the generated register enums require explicit conversion. llvm-svn: 364194
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-245-52/+52
| | | | | | | | | Avoids using a plain unsigned for registers throughoug codegen. Doesn't attempt to change every register use, just something a little more than the set needed to build after changing the return type of MachineOperand::getReg(). llvm-svn: 364191
* Simplify std::lower_bound with llvm::{bsearch,lower_bound}. NFCFangrui Song2019-06-212-8/+3
| | | | llvm-svn: 364006
* [MIPS GlobalISel] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off ↵Fangrui Song2019-06-212-2/+4
| | | | | | builds after D63541 llvm-svn: 364003
* [MIPS GlobalISel] Select integer to floating point conversionsPetar Avramovic2019-06-202-0/+21
| | | | | | | | Select G_SITOFP and G_UITOFP for MIPS32. Differential Revision: https://reviews.llvm.org/D63542 llvm-svn: 363912
* [MIPS GlobalISel] Select floating point to integer conversionsPetar Avramovic2019-06-203-0/+50
| | | | | | | | Select G_FPTOSI and G_FPTOUI for MIPS32. Differential Revision: https://reviews.llvm.org/D63541 llvm-svn: 363911
* [mips] Mark the `lwupc` instruction as MIPS64 R6 onlySimon Atanasyan2019-06-192-3/+3
| | | | | | | | | | The "The MIPS64 Instruction Set Reference Manual" [1] states that the `lwupc` is MIPS64 Release 6 only. It should not be supported for 32-bit CPUs. [1] https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf llvm-svn: 363886
* [mips] Add (GPR|PTR)_64 predicates to PseudoReturn64 and ↵Simon Atanasyan2019-06-191-2/+2
| | | | | | | | | PseudoIndirectHazardBranch64 This patch is one of a series of patches. The goal is to make P5600 scheduler model complete and turn on the `CompleteModel` flag. llvm-svn: 363885
* [mips] Add more strict predicates to the RSQRT_S_MM and TAILCALL_MMSimon Atanasyan2019-06-182-2/+3
| | | | | | | This patch is one of a series of patches. The goal is to make P5600 scheduler model complete and turn on the `CompleteModel` flag. llvm-svn: 363703
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