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| author | Simon Atanasyan <simon@atanasyan.com> | 2019-07-03 12:28:05 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-07-03 12:28:05 +0000 |
| commit | a10bf0939d65c24a63ae081b46ca617fa2cfd581 (patch) | |
| tree | d5d6f088775ff1c5efe4a73660f1f6295b502848 /llvm/lib/Target/Mips | |
| parent | 4d364659f9d76daa74fda78bf7a21bdfc0056460 (diff) | |
| download | bcm5719-llvm-a10bf0939d65c24a63ae081b46ca617fa2cfd581.tar.gz bcm5719-llvm-a10bf0939d65c24a63ae081b46ca617fa2cfd581.zip | |
[mips] Mark general scheduling model as complete
llvm-svn: 365034
Diffstat (limited to 'llvm/lib/Target/Mips')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsScheduleGeneric.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td index 58a7b0b38d2..10393280cf0 100644 --- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td +++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td @@ -24,11 +24,11 @@ def MipsGenericModel : SchedMachineModel { int HighLatency = 37; list<Predicate> UnsupportedFeatures = []; - let CompleteModel = 0; + let CompleteModel = 1; let PostRAScheduler = 1; // FIXME: Remove when all errors have been fixed. - let FullInstRWOverlapCheck = 0; + let FullInstRWOverlapCheck = 1; } let SchedModel = MipsGenericModel in { |
