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authorSimon Atanasyan <simon@atanasyan.com>2019-07-02 10:21:59 +0000
committerSimon Atanasyan <simon@atanasyan.com>2019-07-02 10:21:59 +0000
commit116cf95c00a377ccce7aca7bb48d0017913a2be1 (patch)
treec2d12ad51453cb5107cd9bc9b7749efdbf51e76f /llvm/lib/Target/Mips
parent9df825f4297ff1cd716c8b5fc838166c99d3ee8c (diff)
downloadbcm5719-llvm-116cf95c00a377ccce7aca7bb48d0017913a2be1.tar.gz
bcm5719-llvm-116cf95c00a377ccce7aca7bb48d0017913a2be1.zip
[mips] Map SNOP, NOP to the P5600Nop scheduler resource
llvm-svn: 364899
Diffstat (limited to 'llvm/lib/Target/Mips')
-rw-r--r--llvm/lib/Target/Mips/MipsScheduleP5600.td10
1 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td
index 19d2631a874..0ee6e9e1d85 100644
--- a/llvm/lib/Target/Mips/MipsScheduleP5600.td
+++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td
@@ -59,15 +59,21 @@ def P5600WriteJumpAndLink : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]> {
let Latency = 2;
}
+def P5600Nop : SchedWriteRes<[P5600IssueCTISTD]> {
+ let Latency = 0;
+}
+
+def : InstRW<[P5600Nop], (instrs SSNOP, NOP)>;
+
// b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal,
// jalr, jr.hb, jr
def : InstRW<[P5600WriteJump], (instrs B, BAL, BAL_BR, BEQ, BEQL, BGEZ, BGEZAL,
BGEZALL, BGEZL, BGTZ, BGTZL, BLEZ, BLEZL, BLTZ,
BLTZAL, BLTZALL, BLTZL, BNE, BNEL, BREAK,
- DERET, ERET, ERETNC, J, JR, JR_HB,
+ DERET, ERET, ERet, ERETNC, J, JR, JR_HB,
PseudoIndirectBranch,
PseudoIndirectHazardBranch, PseudoReturn,
- SDBBP, SSNOP, SYSCALL, TAILCALL, TAILCALLREG,
+ SDBBP, SYSCALL, RetRA, TAILCALL, TAILCALLREG,
TAILCALLREGHB, TEQ, TEQI, TGE, TGEI, TGEIU,
TGEU, TLT, TLTI, TLTU, TNE, TNEI, TRAP,
TTLTIU, WAIT, PAUSE)>;
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