diff options
| author | Diana Picus <diana.picus@linaro.org> | 2019-06-27 08:50:53 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2019-06-27 08:50:53 +0000 |
| commit | 69ce1c1319634dbf8bc3d6cb4305efea2da0965f (patch) | |
| tree | 8c69df9e5994613d7bea68f951efe1cb827fd66c /llvm/lib/Target/Mips | |
| parent | 8479240b0a62efa0481f60db81a60f7638079003 (diff) | |
| download | bcm5719-llvm-69ce1c1319634dbf8bc3d6cb4305efea2da0965f.tar.gz bcm5719-llvm-69ce1c1319634dbf8bc3d6cb4305efea2da0965f.zip | |
[GlobalISel] Allow multiple VRegs in ArgInfo. NFC
Allow CallLowering::ArgInfo to contain more than one virtual register.
This is useful when passes split aggregates into several virtual
registers, but need to also provide information about the original type
to the call lowering. Used in follow-up patches.
Differential Revision: https://reviews.llvm.org/D63548
llvm-svn: 364509
Diffstat (limited to 'llvm/lib/Target/Mips')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsCallLowering.cpp | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp index dc4eaf8f1b1..de235d4744c 100644 --- a/llvm/lib/Target/Mips/MipsCallLowering.cpp +++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp @@ -66,6 +66,8 @@ bool MipsCallLowering::MipsHandler::handle( EVT VT = TLI.getValueType(DL, Args[ArgsIndex].Ty); SplitLength = TLI.getNumRegistersForCallingConv(F.getContext(), F.getCallingConv(), VT); + assert(Args[ArgsIndex].Regs.size() == 1 && "Can't handle multple regs yet"); + if (SplitLength > 1) { VRegs.clear(); MVT RegisterVT = TLI.getRegisterTypeForCallingConv( @@ -73,10 +75,11 @@ bool MipsCallLowering::MipsHandler::handle( for (unsigned i = 0; i < SplitLength; ++i) VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT})); - if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Reg, VT)) + if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Regs[0], + VT)) return false; } else { - if (!assign(Args[ArgsIndex].Reg, ArgLocs[ArgLocsIndex], VT)) + if (!assign(Args[ArgsIndex].Regs[0], ArgLocs[ArgLocsIndex], VT)) return false; } } @@ -510,7 +513,9 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, if (Arg.Flags.isByVal() || Arg.Flags.isSRet()) return false; } - if (OrigRet.Reg && !isSupportedType(OrigRet.Ty)) + + assert(OrigRet.Regs.size() == 1 && "Can't handle multple regs yet"); + if (OrigRet.Regs[0] && !isSupportedType(OrigRet.Ty)) return false; MachineFunction &MF = MIRBuilder.getMF(); @@ -595,8 +600,7 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, *STI.getRegBankInfo()); } - if (OrigRet.Reg) { - + if (OrigRet.Regs[0]) { ArgInfos.clear(); SmallVector<unsigned, 8> OrigRetIndices; |
