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* Add more const qualifiers. This fixes build breakage from r59540.Dan Gohman2008-11-181-2/+2
| | | | llvm-svn: 59542
* Const-ify several TargetInstrInfo methods.Dan Gohman2008-10-161-2/+2
| | | | llvm-svn: 57622
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-15/+15
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy ↵Owen Anderson2008-08-261-6/+10
| | | | | | | | | requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
* Convert uses of std::vector in TargetInstrInfo to SmallVector. This change ↵Owen Anderson2008-08-141-5/+4
| | | | | | had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
* Improved asm inline for hi,lo resultsBruno Cardoso Lopes2008-08-021-11/+23
| | | | | | | | Added hi,lo registers to be used,def implicitly. This provides better handle of instructions which use hi/lo. Fixes a small BranchAnalysis bug llvm-svn: 54274
* Added floating point lowering for setcc and brcond.Bruno Cardoso Lopes2008-07-281-7/+51
| | | | | | | Fixed COMM asm directive usage. ConstantPool using custom FourByteConstantSection. llvm-svn: 54139
* Added Subtarget support into RegisterInfoBruno Cardoso Lopes2008-07-141-2/+3
| | | | | | | | | | | | Added HasABICall and HasAbsoluteCall (equivalent to gcc -mabicall and -mno-shared). HasAbsoluteCall is not implemented but HasABICall is the default for o32 ABI. Now, both should help into a more accurate relocation types implementation. Added IsLinux is needed to choose between asm directives. Instruction name strings cleanup. AsmPrinter improved. llvm-svn: 53551
* Fixe typos and 80 column size problemsBruno Cardoso Lopes2008-07-091-1/+2
| | | | llvm-svn: 53272
* Pool-allocation for MachineInstrs, MachineBasicBlocks, andDan Gohman2008-07-071-6/+6
| | | | | | | | | | | MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
* Several changes to Mips backend, experimental fp support being the mostBruno Cardoso Lopes2008-07-051-138/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
* - Remove calls to copyKillDeadInfo which is an N^2 function. Instead, ↵Evan Cheng2008-07-031-7/+11
| | | | | | | | propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
* It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵Evan Cheng2008-02-081-1/+2
| | | | | | the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-7/+5
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner2008-01-071-2/+2
| | | | llvm-svn: 45680
* Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner2008-01-071-1/+1
| | | | | | | | | | | | | | | that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-0/+31
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-0/+65
| | | | llvm-svn: 45484
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-011-1/+1
| | | | | | | | | | a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-0/+17
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-7/+7
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-1/+1
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Add lengthof and endof templates that hide a lot of sizeof computations.Owen Anderson2007-09-071-1/+2
| | | | | | Patch by Sterling Stein! llvm-svn: 41758
* Added Branch Analysis support Bruno Cardoso Lopes2007-08-181-5/+234
| | | | | | Added InsertNoop support llvm-svn: 41153
* Initial Mips support, here we go! =)Bruno Cardoso Lopes2007-06-061-0/+114
- Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461
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