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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [mips] Sink PredicateControl further down the class hierarchy.Simon Dardis2018-05-301-1/+1
| | | | | | | | | | | | | | | | Previously PredicateControl in some cases was a member of <X>Inst classes for some X (DSP, EVA) or was in more irregular place in the hierarchry for any given instruction. This patch moves PredicateControl down to the root so that it is consistently available. Then correct the base class of microMIPS instructions as using EncodingPredicates instead of the general Predicates field of Instruction. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D47526 llvm-svn: 333536
* [mips] Split out ASEPredicate from InsnPredicates (NFC)Simon Dardis2018-03-121-5/+5
| | | | | | | | | | | This simplifies tagging instructions with the correct ISA and ASE, albeit making instruction definitions a bit more verbose. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44299 llvm-svn: 327265
* [mips] Spectre variant two mitigation for MIPSR2Simon Dardis2018-02-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides mitigation for CVE-2017-5715, Spectre variant two, which affects the P5600 and P6600. It implements the LLVM part of -mindirect-jump=hazard. It is _not_ enabled by default for the P5600. The migitation strategy suggested by MIPS for these processors is to use hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard barrier variants of the 'jalr' and 'jr' instructions respectively. These instructions impede the execution of instruction stream until architecturally defined hazards (changes to the instruction stream, privileged registers which may affect execution) are cleared. These instructions in MIPS' designs are not speculated past. These instructions are used with the attribute +use-indirect-jump-hazard when branching indirectly and for indirect function calls. These instructions are defined by the MIPS32R2 ISA, so this mitigation method is not compatible with processors which implement an earlier revision of the MIPS ISA. Performance benchmarking of this option with -fpic and lld using -z hazardplt shows a difference of overall 10%~ time increase for the LLVM testsuite. Certain benchmarks such as methcall show a substantially larger increase in time due to their nature. Reviewers: atanasyan, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D43486 llvm-svn: 325653
* [mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and ↵Hrvoje Varga2016-05-131-0/+4
| | | | | | | | MULSAQ_S.W.PH instructions Differential Revision: http://reviews.llvm.org/D14117 llvm-svn: 269408
* [mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV ↵Zlatko Buljan2015-12-181-5/+10
| | | | | | | | and WRDSP instructions Differential Revision: http://reviews.llvm.org/D14429 llvm-svn: 255991
* [mips][microMIPS] Implement DPA.W.PH, DPAQ_S.W.PH, DPAQ_SA.L.W, ↵Zlatko Buljan2015-10-151-0/+4
| | | | | | | | DPAQX_S.W.PH, DPAQX_SA.W.PH, DPAU.H.QBL, DPAU.H.QBR and DPAX.W.PH instructions Differential Revision: http://reviews.llvm.org/D13376 llvm-svn: 250382
* [mips][micromips] Initial support for micrmomips DSP instructions and ↵Zoran Jovanovic2015-10-121-1/+20
| | | | | | | | addu.qb implementation Differential Revision: http://reviews.llvm.org/D12798 llvm-svn: 250058
* Make it possible for the Subtarget to change between functionEric Christopher2014-07-101-2/+2
| | | | | | | | passes in the mips back end. This, unfortunately, required a bit of churn in the various predicates to use a pointer rather than a reference. llvm-svn: 212744
* [mips] DSP-ASE move from HI/LO register instructions.Akira Hatanaka2013-04-181-0/+27
| | | | llvm-svn: 179739
* [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass Akira Hatanaka2012-12-201-2/+3
| | | | | | parameter. llvm-svn: 170661
* MIPS DSP: other miscellaneous instructions.Akira Hatanaka2012-09-281-0/+55
| | | | llvm-svn: 164845
* MIPS DSP: ADDUH.QB instruction sub-class.Akira Hatanaka2012-09-281-0/+15
| | | | llvm-svn: 164840
* MIPS DSP: ABSQ_S.PH instruction sub-class.Akira Hatanaka2012-09-271-0/+27
| | | | llvm-svn: 164787
* MIPS DSP: SHLL.QB instruction sub-class.Akira Hatanaka2012-09-271-0/+15
| | | | llvm-svn: 164786
* MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR).Akira Hatanaka2012-09-271-0/+12
| | | | llvm-svn: 164756
* MIPS DSP: CMPU.EQ.QB instruction sub-class.Akira Hatanaka2012-09-271-0/+42
| | | | llvm-svn: 164755
* MIPS DSP: ADDU.QB instruction sub-class.Akira Hatanaka2012-09-271-0/+28
| | | | llvm-svn: 164754
* MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos ↵Akira Hatanaka2012-09-271-0/+10
| | | | | | Field instruction. llvm-svn: 164751
* MIPS DSP: all the remaining instructions which read or write accumulators.Akira Hatanaka2012-09-271-0/+64
| | | | llvm-svn: 164750
* MIPS DSP: add support for extract-word instructions.Akira Hatanaka2012-09-271-0/+16
| | | | llvm-svn: 164749
* MIPS DSP: Add predicates and instruction template.Akira Hatanaka2012-09-221-0/+25
llvm-svn: 164434
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