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authorAkira Hatanaka <ahatanaka@mips.com>2012-09-27 19:05:08 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2012-09-27 19:05:08 +0000
commit892b1046c6b8893014c256398bb46c93c3cb91f7 (patch)
tree072cd048d2fe5d2471c71759bdef586dc9c7a167 /llvm/lib/Target/Mips/MipsDSPInstrFormats.td
parentc2081d1c19f71e1264e33e91425249fc8a4325f2 (diff)
downloadbcm5719-llvm-892b1046c6b8893014c256398bb46c93c3cb91f7.tar.gz
bcm5719-llvm-892b1046c6b8893014c256398bb46c93c3cb91f7.zip
MIPS DSP: SHLL.QB instruction sub-class.
llvm-svn: 164786
Diffstat (limited to 'llvm/lib/Target/Mips/MipsDSPInstrFormats.td')
-rw-r--r--llvm/lib/Target/Mips/MipsDSPInstrFormats.td15
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsDSPInstrFormats.td b/llvm/lib/Target/Mips/MipsDSPInstrFormats.td
index 2c6e767cf36..b01da9bfa1e 100644
--- a/llvm/lib/Target/Mips/MipsDSPInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsDSPInstrFormats.td
@@ -99,6 +99,21 @@ class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
let Inst{5-0} = 0b010001;
}
+// SHLL.QB sub-class format.
+class SHLL_QB_FMT<bits<5> op> : DSPInst {
+ bits<5> rd;
+ bits<5> rt;
+ bits<5> rs_sa;
+
+ let Opcode = SPECIAL3_OPCODE.V;
+
+ let Inst{25-21} = rs_sa;
+ let Inst{20-16} = rt;
+ let Inst{15-11} = rd;
+ let Inst{10-6} = op;
+ let Inst{5-0} = 0b010011;
+}
+
// DPA.W.PH sub-class format.
class DPA_W_PH_FMT<bits<5> op> : DSPInst {
bits<2> ac;
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