summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Mips/MipsDSPInstrFormats.td
diff options
context:
space:
mode:
authorAkira Hatanaka <ahatanaka@mips.com>2012-09-27 19:09:21 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2012-09-27 19:09:21 +0000
commita9183eda74085de82e7c9ad1d2933a60b8ffae43 (patch)
treeda1cafa888f14d809586c272661bd978880a8000 /llvm/lib/Target/Mips/MipsDSPInstrFormats.td
parent892b1046c6b8893014c256398bb46c93c3cb91f7 (diff)
downloadbcm5719-llvm-a9183eda74085de82e7c9ad1d2933a60b8ffae43.tar.gz
bcm5719-llvm-a9183eda74085de82e7c9ad1d2933a60b8ffae43.zip
MIPS DSP: ABSQ_S.PH instruction sub-class.
llvm-svn: 164787
Diffstat (limited to 'llvm/lib/Target/Mips/MipsDSPInstrFormats.td')
-rw-r--r--llvm/lib/Target/Mips/MipsDSPInstrFormats.td27
1 files changed, 27 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsDSPInstrFormats.td b/llvm/lib/Target/Mips/MipsDSPInstrFormats.td
index b01da9bfa1e..450d021fa26 100644
--- a/llvm/lib/Target/Mips/MipsDSPInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsDSPInstrFormats.td
@@ -99,6 +99,33 @@ class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
let Inst{5-0} = 0b010001;
}
+// ABSQ_S.PH sub-class format.
+class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
+ bits<5> rd;
+ bits<5> rt;
+
+ let Opcode = SPECIAL3_OPCODE.V;
+
+ let Inst{25-21} = 0;
+ let Inst{20-16} = rt;
+ let Inst{15-11} = rd;
+ let Inst{10-6} = op;
+ let Inst{5-0} = 0b010010;
+}
+
+
+class REPL_FMT<bits<5> op> : DSPInst {
+ bits<5> rd;
+ bits<10> imm;
+
+ let Opcode = SPECIAL3_OPCODE.V;
+
+ let Inst{25-16} = imm;
+ let Inst{15-11} = rd;
+ let Inst{10-6} = op;
+ let Inst{5-0} = 0b010010;
+}
+
// SHLL.QB sub-class format.
class SHLL_QB_FMT<bits<5> op> : DSPInst {
bits<5> rd;
OpenPOWER on IntegriCloud