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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [mips] Support sigrie instructionSimon Atanasyan2018-11-061-0/+11
| | | | | | | | | The `sigrie` instruction signals a Reserved Instruction Exception. This patch adds support for assembling / disassembling the instruction. Differential Revision: http://reviews.llvm.org/D53861 llvm-svn: 346230
* [mips] Add licensing information of the microMIPS tablegen files. (NFC)Simon Dardis2018-06-151-0/+13
| | | | llvm-svn: 334827
* [mips] Sink PredicateControl further down the class hierarchy.Simon Dardis2018-05-301-4/+4
| | | | | | | | | | | | | | | | Previously PredicateControl in some cases was a member of <X>Inst classes for some X (DSP, EVA) or was in more irregular place in the hierarchry for any given instruction. This patch moves PredicateControl down to the root so that it is consistently available. Then correct the base class of microMIPS instructions as using EncodingPredicates instead of the general Predicates field of Instruction. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D47526 llvm-svn: 333536
* [mips] Move conditional moves out of isCodeGenOnlySimon Dardis2018-05-091-2/+2
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46389 llvm-svn: 331863
* [mips] Add support for Virtualization ASEPetar Jovanovic2018-04-271-0/+36
| | | | | | | | | | | | | | | | | | | This includes Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0, Assembler directives: .set virt, .set novirt, .module virt, .module novirt Attribute: virt .MIPS.abiflags: VZ (0x100) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D44905 llvm-svn: 331024
* [mips] Correct the definitions of some control instructionsSimon Dardis2018-04-261-1/+1
| | | | | | | | | | | | | | Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
* [mips] Fix the definition of sync, synciSimon Dardis2018-04-251-2/+3
| | | | | | | | | | Also, fix the disassembly of synci for microMIPS. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45870 llvm-svn: 330810
* [mips] Correct the definitions of the unaligned word memory operation ↵Simon Dardis2018-04-191-2/+2
| | | | | | | | | | | | | | | | instructions These instructions lacked the correct predicates, were not marked as loads and stores and lacked the proper instruction mapping information. In the case of microMIPS sw(l|r)e (EVA) these instructions were using the load EVA description. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45626 llvm-svn: 330326
* [mips] Define certain instructions in microMIPS32r3Stefan Maksimovic2018-02-081-1/+0
| | | | | | | | | | | | | | | | | | | | Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
* [mips] Include EVA instructions in Std2MicroMips mapping tablesAleksandar Beserminji2018-02-011-1/+1
| | | | | | | | | This patch includes EVA instructions in the Std2MicroMips mapping tables, which is required for direct object emission. Differential Revision: https://reviews.llvm.org/D41771 llvm-svn: 323958
* [mips][micromips] Fix (dis)assembly of bc1(t|f)Simon Dardis2017-10-161-1/+2
| | | | | | | | | | | | Previously these instructions were marked codegen only and had an under-specified instruction description that did not record the fcc register. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D38847 llvm-svn: 315905
* [mips] Correct c.cond.fmt instruction definition.Simon Dardis2017-01-161-1/+6
| | | | | | | | | | | | | | | Permit explicit $fcc<X> operand in c.cond.fmt instruction. Add c.cond.fmt to the MIPS to microMIPS instruction mapping table. Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for c.cond.fmt, bc1t, bc1f. Reviewers: seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24510 llvm-svn: 292117
* [mips] synci microMIPS instruction definition.Simon Dardis2016-10-241-0/+11
| | | | | | | | | | | | | Add synci to the microMIPS instruction definitions, mark the MIPS sync & synci as not being part of microMIPS. This does not cover the sync instruction alias, as that will be handled with a different patch. Add sync to the valid tests for microMIPS. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D25795 llvm-svn: 284962
* Revert "[mips] Fix c.<cc>.<fmt> instruction definition."Simon Dardis2016-09-091-17/+0
| | | | | | | This reverts commit r281022. Mips buildbot broke, due to unhandled register class FCC. llvm-svn: 281033
* [mips] Fix c.<cc>.<fmt> instruction definition.Simon Dardis2016-09-091-0/+17
| | | | | | | | | | | | | | | As part of this effort, remove MipsFCmp nodes and use tablegen patterns rather than custom lowering through C++. Unexpectedly, this improves codesize for microMIPS as previous floating point setcc expansions would materialize 0 and 1 into GPRs before using the relevant mov[tf].[sd] instruction. Now $zero is used directly. Reviewers: dsanders, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23118 llvm-svn: 281022
* [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructionsHrvoje Varga2016-08-041-0/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D22347 llvm-svn: 277719
* [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV ↵Hrvoje Varga2016-06-271-1/+1
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16625 llvm-svn: 273850
* [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add ↵Zlatko Buljan2016-05-181-3/+4
| | | | | | | | CodeGen support Differential Revision: http://reviews.llvm.org/D15418 llvm-svn: 269883
* [mips][microMIPS] Revert commit r267137Hrvoje Varga2016-04-251-0/+1
| | | | | | Commit r267137 was the reason for failing tests in LLVM test suite. llvm-svn: 267419
* [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructionsHrvoje Varga2016-04-221-1/+0
| | | | | | Differential Revision: http://reviews.llvm.org/D19354 llvm-svn: 267137
* [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructionsZlatko Buljan2015-11-121-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D11406 llvm-svn: 252885
* [mips][microMIPS] Implement LLE and SCE instructionsHrvoje Varga2015-10-151-0/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D11630 llvm-svn: 250379
* [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructionsHrvoje Varga2015-10-151-0/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D11631 llvm-svn: 250377
* [mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and ↵Zoran Jovanovic2015-09-161-0/+31
| | | | | | | | SWE instructions Differential Revision: http://reviews.llvm.org/D9189 llvm-svn: 247780
* [mips][microMIPS] Implement CACHEE and PREFE instructionsZoran Jovanovic2015-09-091-0/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D11628 llvm-svn: 247125
* [mips][microMIPS] Implement movep instructionZoran Jovanovic2015-02-101-0/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
* [mips][microMIPS] Implement LWGP instructionJozef Kolek2015-01-281-0/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D6650 llvm-svn: 227325
* [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction BJozef Kolek2015-01-211-0/+9
| | | | | | | | | | | | | | Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226657
* [mips][microMIPS] Implement ADDIUPC instructionJozef Kolek2015-01-211-0/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D6582 llvm-svn: 226656
* Reverted revision 226577.Jozef Kolek2015-01-201-9/+0
| | | | llvm-svn: 226595
* [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction BJozef Kolek2015-01-201-0/+9
| | | | | | | | | | | | | | Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226577
* [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructionsJozef Kolek2015-01-121-0/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D5271 llvm-svn: 225627
* [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructionsJozef Kolek2014-12-231-0/+26
| | | | | | Differential Revision: http://reviews.llvm.org/D5204 llvm-svn: 224785
* [mips][microMIPS] Implement LWSP and SWSP instructionsJozef Kolek2014-12-231-0/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D6416 llvm-svn: 224771
* [mips][microMIPS] Implement SWM16 and LWM16 instructionsZoran Jovanovic2014-11-271-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D5579 llvm-svn: 222901
* [mips][microMIPS] Implement BREAK16 and SDBBP16 instructionsJozef Kolek2014-11-271-0/+9
| | | | | | | | Patch by Radovan Obradovic. Differential Revision: http://reviews.llvm.org/D5048 llvm-svn: 222900
* [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructionsJozef Kolek2014-11-241-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D5122 llvm-svn: 222653
* [mips][micromips] Implement SWM32 and LWM32 instructionsZoran Jovanovic2014-11-191-0/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
* [mips][microMIPS] Implement LWXS instruction.Jozef Kolek2014-11-191-0/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D5407 llvm-svn: 222348
* [mips][microMIPS] Implement SDBBP and RDHWR instructions.Jozef Kolek2014-11-191-0/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D5240 llvm-svn: 222347
* [mips][microMIPS] Implement ANDI16 instructionZoran Jovanovic2014-11-051-0/+13
| | | | llvm-svn: 221367
* Reverted revisions 221351, 221352 and 221353.Zoran Jovanovic2014-11-051-13/+0
| | | | llvm-svn: 221354
* [mips][microMIPS] Implement ANDI16 instructionZoran Jovanovic2014-11-051-0/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D5163 llvm-svn: 221351
* [mips][microMIPS] Implement ADDIUR1SP instructionZoran Jovanovic2014-10-231-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D5153 llvm-svn: 220477
* ps][microMIPS] Implement ADDIUR2 instructionZoran Jovanovic2014-10-231-0/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D5151 llvm-svn: 220476
* ps][microMIPS] Implement LI16 instructionZoran Jovanovic2014-10-231-0/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D5149 llvm-svn: 220475
* [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructionsZoran Jovanovic2014-10-231-0/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D5774 llvm-svn: 220474
* [mips][microMIPS] Implement ADDU16 and SUBU16 instructionsZoran Jovanovic2014-10-211-0/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D5118 llvm-svn: 220276
* [mips][microMIPS] Implement AND16, NOT16, OR16 and XOR16 instructionsZoran Jovanovic2014-10-211-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D5117 llvm-svn: 220275
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