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* [mips][microMIPS] Implement LWSP and SWSP instructionsJozef Kolek2014-12-231-0/+21
| | | | | | Differential Revision: http://reviews.llvm.org/D6416 llvm-svn: 224771
* Fix UBSan bootstrap: replace shift of negative value with multiplication.Alexey Samsonov2014-12-231-1/+1
| | | | llvm-svn: 224752
* The single check for N64 inside MipsDisassemblerBase's subclasses is ↵Vladimir Medic2014-12-161-4/+4
| | | | | | actually wrong. It should be testing for FeatureGP64bit.There are no functional changes. llvm-svn: 224339
* [mips][microMIPS] Implement SWP and LWP instructionsZoran Jovanovic2014-12-161-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D5667 llvm-svn: 224338
* Add disassembler tests for mips3 platform. There are no functional changes.Vladimir Medic2014-12-151-1/+2
| | | | llvm-svn: 224253
* The andi16, addiusp and jraddiusp micromips instructions were missing ↵Vladimir Medic2014-12-011-0/+39
| | | | | | dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. llvm-svn: 223006
* [mips][microMIPS] Implement SWM16 and LWM16 instructionsZoran Jovanovic2014-11-271-0/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D5579 llvm-svn: 222901
* [mips] Add synci instruction.Daniel Sanders2014-11-271-0/+20
| | | | | | | | | | | | | | Patch by Amaury Pouly Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6421 llvm-svn: 222899
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-271-0/+60
| | | | | | | | LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-261-1/+62
| | | | | | | | LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
* [mips][microMIPS] Implement 16-bit instructions registers including ZERO ↵Jozef Kolek2014-11-241-0/+12
| | | | | | | | | | instead of S0 Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17. Differential Revision: http://reviews.llvm.org/D5780 llvm-svn: 222652
* [mips][microMIPS] Implement disassembler support for 16-bit instructionsJozef Kolek2014-11-241-11/+54
| | | | | | | | | | | With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
* [mips][micromips] Implement SWM32 and LWM32 instructionsZoran Jovanovic2014-11-191-5/+43
| | | | | | Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
* Pass an ArrayRef to MCDisassembler::getInstruction.Rafael Espindola2014-11-121-15/+11
| | | | | | | | | | | | With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t> instead of a MemoryObject. Even on X86 there is a maximum size an instruction can have. Given that, it seems way simpler and more efficient to just pass an ArrayRef to the disassembler instead of a MemoryObject and have it do a virtual call every time it wants some extra bytes. llvm-svn: 221751
* Misc style fixes. NFC.Rafael Espindola2014-11-101-78/+53
| | | | | | | | | | | | | This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
* [mips][microMIPS] Implement microMIPS 16-bit instructions registersZoran Jovanovic2014-10-211-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D5116 llvm-svn: 220273
* [mips] Fix disassembly of [ls][wd]c[23], cache, and pref ↵Daniel Sanders2014-10-011-0/+66
| | | | | | | | Fixes PR21015, and PR20993. Patch by Jun Koi llvm-svn: 218745
* Fix left shifts of negative values in MipsDisassembler.Alexey Samsonov2014-09-021-15/+15
| | | | | | This bug was reported by UBSan. llvm-svn: 216920
* Prune dependency to MC from each target disassembler.NAKAMURA Takumi2014-07-241-1/+1
| | | | llvm-svn: 213856
* Update library dependencies.NAKAMURA Takumi2014-07-241-1/+1
| | | | llvm-svn: 213832
* [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders2014-07-141-17/+0
| | | | | | | | | | | | | | FP64 moves Summary: This is similar to r210771 which did the same thing for MTHC1. Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the wrong definitions. Differential Revision: http://reviews.llvm.org/D4483 llvm-svn: 212936
* [mips][mips64r6] Add BLTC and BLTUC instructionsZoran Jovanovic2014-06-181-4/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D3923 llvm-svn: 211167
* [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.Daniel Sanders2014-06-161-0/+26
| | | | | | | | | | | | | | | | | | | | | Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
* [mips] Add cache and pref instructionsDaniel Sanders2014-06-131-8/+24
| | | | | | | | | | | | | | | | | | | Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 llvm-svn: 210900
* [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available ↵Daniel Sanders2014-06-121-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
* [mips][mips64r6] Add bgec and bgeuc instructionsZoran Jovanovic2014-06-121-2/+56
| | | | | | Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
* [mips][mips64r6] Add LDPC instructionZoran Jovanovic2014-06-091-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D3822 llvm-svn: 210460
* [mips][mips64r6] Add b[on]vcDaniel Sanders2014-05-221-10/+243
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
* [mips][mips64r6] Add bc[12](eq|ne)zDaniel Sanders2014-05-211-0/+17
| | | | | | | | | | | | Summary: Depends on D3691 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3760 llvm-svn: 209292
* [mips][mips64r6] Add compact branch instructionsZoran Jovanovic2014-05-161-0/+30
| | | | | | Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
* [mips][mips64r6] Add addiupc, aluipc, and auipcDaniel Sanders2014-05-151-0/+9
| | | | | | | | | | | | | | | | Summary: No support for symbols in place of the immediate yet since it requires new relocations. Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3689 llvm-svn: 208858
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-12/+12
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
* [Modules] Make Support/Debug.h modular. This requires it to not changeChandler Carruth2014-04-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | behavior based on other files defining DEBUG_TYPE, which means it cannot define DEBUG_TYPE at all. This is actually better IMO as it forces folks to define relevant DEBUG_TYPEs for their files. However, it requires all files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't already. I've updated all such files in LLVM and will do the same for other upstream projects. This still leaves one important change in how LLVM uses the DEBUG_TYPE macro going forward: we need to only define the macro *after* header files have been #include-ed. Previously, this wasn't possible because Debug.h required the macro to be pre-defined. This commit removes that. By defining DEBUG_TYPE after the includes two things are fixed: - Header files that need to provide a DEBUG_TYPE for some inline code can do so by defining the macro before their inline code and undef-ing it afterward so the macro does not escape. - We no longer have rampant ODR violations due to including headers with different DEBUG_TYPE definitions. This may be mostly an academic violation today, but with modules these types of violations are easy to check for and potentially very relevant. Where necessary to suppor headers with DEBUG_TYPE, I have moved the definitions below the includes in this commit. I plan to move the rest of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big enough. The comments in Debug.h, which were hilariously out of date already, have been updated to reflect the recommended practice going forward. llvm-svn: 206822
* [MC] Require an MCContext when constructing an MCDisassembler.Lang Hames2014-04-151-18/+21
| | | | | | | | | | | | | | | | This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
* LLVMBuild.txt: Reformat.NAKAMURA Takumi2014-04-101-1/+1
| | | | llvm-svn: 205961
* [mips] Rewrite MipsAsmParser and MipsOperand.Daniel Sanders2014-04-011-1/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
* Revert: [mips] Rewrite MipsAsmParser and MipsOperand.' due to buildbot ↵Daniel Sanders2014-03-311-51/+1
| | | | | | | | errors in lld tests. It's currently unable to parse 'sym + imm' without surrounding parenthesis. llvm-svn: 205237
* [mips] Rewrite MipsAsmParser and MipsOperand.Daniel Sanders2014-03-311-1/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205229
* Cleaning up a bunch of pre-Visual C++ 2012 build hacks.Yaron Keren2014-03-041-8/+0
| | | | llvm-svn: 202806
* Fixed operand of SC microMIPS instruction.Zoran Jovanovic2014-02-281-0/+3
| | | | llvm-svn: 202526
* [mips][msa] Fix issue with immediate fields of LD/ST instructionsMatheus Almeida2013-12-051-1/+31
| | | | | | | | | not being correctly encoded/decoded. In more detail, immediate fields of LD/ST instructions should be divided/multiplied by the size of the data format before encoding and after decoding, respectively. llvm-svn: 196494
* [CMake] Let add_public_tablegen_target responsible to provide dependency to ↵NAKAMURA Takumi2013-11-281-2/+0
| | | | | | | | | CommonTableGen. add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS. LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope. llvm-svn: 195927
* [CMake] Prune include_directories() in llvm/lib/Target. add_llvm_target() ↵NAKAMURA Takumi2013-11-281-2/+0
| | | | | | sets them. llvm-svn: 195921
* [mips][msa] Fix immediate value of LSA instruction as it was being wrongly ↵Matheus Almeida2013-11-181-0/+16
| | | | | | | | | encoded. The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field. llvm-svn: 195004
* Support for microMIPS branch instructions.Zoran Jovanovic2013-11-041-0/+17
| | | | llvm-svn: 193992
* Support for microMIPS jump instructionsZoran Jovanovic2013-10-291-0/+15
| | | | llvm-svn: 193623
* [mips][msa] Direct Object Emission support for LD/ST instructions.Matheus Almeida2013-10-211-0/+19
| | | | llvm-svn: 193082
* [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. Matheus Almeida2013-10-211-0/+17
| | | | | | | | These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
* [mips][msa] Direct Object Emission for 3R instructions.Jack Carter2013-09-261-0/+17
| | | | | | | | This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
* [mips][msa] Direct Object Emission support for the MSA instruction set. Jack Carter2013-09-251-0/+51
| | | | | | | | | | In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
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