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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-06-18 14:36:00 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-06-18 14:36:00 +0000 |
| commit | 5c14b06940be17fe2023f1eb5998ceaa25fe6c5a (patch) | |
| tree | d78b2faecfbd1cbcdea06ecbc5b43f41de2ee158 /llvm/lib/Target/Mips/Disassembler | |
| parent | b87f1efc5f5b39e0a7665b1fabb7b6260bbf6fab (diff) | |
| download | bcm5719-llvm-5c14b06940be17fe2023f1eb5998ceaa25fe6c5a.tar.gz bcm5719-llvm-5c14b06940be17fe2023f1eb5998ceaa25fe6c5a.zip | |
[mips][mips64r6] Add BLTC and BLTUC instructions
Differential Revision: http://reviews.llvm.org/D3923
llvm-svn: 211167
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler')
| -rw-r--r-- | llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 908166f0a7b..902b87759dc 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -576,6 +576,8 @@ static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, // BLTZC if rs == rt && rt != 0 // BLTC if rs != rt && rs != 0 && rt != 0 + bool HasRs = false; + InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; @@ -586,8 +588,14 @@ static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, MI.setOpcode(Mips::BGTZC); else if (Rs == Rt) MI.setOpcode(Mips::BLTZC); - else - return MCDisassembler::Fail; // FIXME: BLTC is not implemented yet. + else { + MI.setOpcode(Mips::BLTC); + HasRs = true; + } + + if (HasRs) + MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, + Rs))); MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); @@ -627,8 +635,11 @@ static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, } else if (Rs == Rt) { MI.setOpcode(Mips::BLTZALC); HasRs = true; - } else - return MCDisassembler::Fail; // BLTUC not implemented yet + } else { + MI.setOpcode(Mips::BLTUC); + HasRs = true; + HasRt = true; + } if (HasRs) MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, |
