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* Revert r277988: [mips][ias] Fix all the hacks related to MIPS-specific unary ↵Daniel Sanders2016-08-081-70/+163
| | | | | | | | operators (%hi/%lo/%gp_rel/etc.). It seems that MSVC doesn't like std::tie(). llvm-svn: 277990
* [mips][ias] Fix all the hacks related to MIPS-specific unary operators ↵Daniel Sanders2016-08-081-163/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (%hi/%lo/%gp_rel/etc.). Summary: They are now lexed as a single token on targets where MCAsmInfo::HasMipsExpressions is true and then parsed in a similar way to the '~' operator as part of MCExpr::parseExpression. As a result: * expressions and immediates no longer have different parsing rules. The difference is now solely down to whether evaluateAsAbsolute() succeeds. * %hi(%neg(%gp_rel(x))) are no longer parsed as a single operator and decomposed into the three MipsMCExpr nodes. They are parsed directly as three MipsMCExpr nodes. * parseMemOperand no longer needs to eat all the surrounding parenthesis to get at the outermost operator to make this work * %hi(%neg(%gp_rel(x))) and %lo(%neg(%gp_rel(x))) are no longer the only 3-in-1 relocs that parse for N64. They're still the only combinations that are permitted in relocatable expressions though. Fixing that should be a later patch. * We no longer need to list all the tokens that can occur as the first token of an expression or immediate. test/MC/Mips/expr1.s: This change also prevents the incorrect lowering of %lo(2*4)+foo to %lo(8+foo) which is not an equivalent expression (the difference is whether foo is truncated to 16-bit or not) and the test has been updated to account for the macro expansion the correct expression requires. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D23110 llvm-svn: 277988
* [mips] Fix a warning that occurs on some gcc 4.9.2's but not all of them.Daniel Sanders2016-07-281-4/+4
| | | | llvm-svn: 276993
* [mips][ias] Check '$rs = $rd' constraints when both registers are in AsmText.Daniel Sanders2016-07-271-37/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is one possible solution to the problem of ignoring constraints that Simon raised in D21473 but it's a bit of a hack. The integrated assembler currently ignores violations of the tied register constraints when the operands involved in a tie are both present in the AsmText. For example, 'dati $rs, $rt, $imm' with the '$rs = $rt' will silently replace $rt with $rs. So 'dati $2, $3, 1' is processed as if the user provided 'dati $2, $2, 1' without any diagnostic being emitted. This is difficult to solve properly because there are multiple parts of the matcher that are silently forcing these constraints to be met. Tied operands are rendered to instructions by cloning previously rendered operands but this is unnecessary because the matcher was already instructed to render the operand it would have cloned. This is also unnecessary because earlier code has already replaced the MCParsedOperand with the one it was tied to (so the parsed input is matched as if it were 'dati <RegIdx 2>, <RegIdx 2>, <Imm 1>'). As a result, it looks like fixing this properly amounts to a rewrite of the tied operand handling which affects all targets. This patch however, merely inserts a checking hook just before the substitution of MCParsedOperands and the Mips target overrides it. It's not possible to accurately check the registers are the same this early (because numeric registers haven't been bound to a register class yet) so it cheats a bit and checks that the tokens that produced the operand are lexically identical. This works because tied registers need to have the same register class but it does have a flaw. It will reject 'dati $4, $a0, 1' for violating the constraint even though $a0 ends up as the same register as $4. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D21994 llvm-svn: 276867
* [mips] MIPS64R6 compact branch supportSimon Dardis2016-07-261-3/+18
| | | | | | | | | | | | | MIPS64R6 compact branch support. As the MIPS LLVM backend uses distinct MachineInstrs for certain 32 and 64 bit instructions (e.g. BEQ & BEQ64) that map to the same instruction, extend compact branch support for the corresponding 64bit branches. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D20164 llvm-svn: 276739
* [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and ↵Zlatko Buljan2016-07-111-4/+11
| | | | | | | | SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
* [mips][ias] Remove k_PhysReg since it's not possible to create an operand of ↵Daniel Sanders2016-07-051-20/+7
| | | | | | | | | | | | this kind. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21986 llvm-svn: 274547
* Revert r274536: [mips][ias] Don't break apart and reconstruct StringRef's ↵Daniel Sanders2016-07-051-4/+6
| | | | | | | | for k_Token. NFC. It turns out that MSVC requires this. llvm-svn: 274538
* [mips][ias] Don't break apart and reconstruct StringRef's for k_Token. NFC.Daniel Sanders2016-07-051-6/+4
| | | | llvm-svn: 274536
* [mips][ias] Integers are not registers.Daniel Sanders2016-06-231-6/+0
| | | | | | | | | | | | | | | | | | | Summary: When parseAnyRegister() encounters a symbol alias, it parses integers and adds a corresponding expression to the operand list. This is clearly wrong since the only operands that parseAnyRegister() should be accepting are registers. It's not clear why this code was added and there are no test cases that cover it. I think it might be leftover from when searchSymbolAlias() was more widely used. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21377 llvm-svn: 273555
* Delete more dead code.Rafael Espindola2016-06-211-51/+0
| | | | | | Found by gcc 6. llvm-svn: 273322
* Delete some dead code.Rafael Espindola2016-06-211-25/+0
| | | | | | Found by gcc 6. llvm-svn: 273303
* [mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructionsHrvoje Varga2016-06-091-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
* [mips] Implement 'la' macro in PIC mode for O32.Daniel Sanders2016-06-031-7/+77
| | | | | | | | | | | | | | | | Summary: N32 support will follow in a later patch since the symbol version of 'la' incorrectly believes N32 to have 64-bit pointers and rejects it early. This fixes the three incorrectly expanded 'la' macros found in bionic. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20820 llvm-svn: 271644
* [mips] Enforce compact branch register restrictionsSimon Dardis2016-05-311-10/+54
| | | | | | | | | | | | | | | Enforce compact branch register restrictions such as the use of the zero register, both operands being the same register. Emit clear error in such cases as the issue is subtle. For bovc and bnvc, silently fixup such cases when emitting objects directly, like LLVM started doing in rL269899. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D20475 llvm-svn: 271301
* [mips] Weaken asm predicate for memory offsetsSimon Dardis2016-05-271-3/+7
| | | | | | | | | | | | The isMemWithSimmOffset predicate rejects relocations which is incorrect behaviour. Linkers and other tools should handle|warn|error when the field overflows. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D20727 llvm-svn: 270995
* Avoid some copies by using const references.Benjamin Kramer2016-05-271-1/+1
| | | | | | | clang-tidy's performance-unnecessary-copy-initialization with some manual fixes. No functional changes intended. llvm-svn: 270988
* [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructionsZlatko Buljan2016-05-191-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D18352 llvm-svn: 270030
* Don't pass a Reloc::Model to MC.Rafael Espindola2016-05-181-2/+1
| | | | | | | | | | | | MC only needs to know if the output is PIC or not. It never has to decide about creating GOTs and PLTs for example. The only thing that MC itself uses this information for is expanding "macros" in sparc and mips. The rest I am pretty sure could be moved to CodeGen. This is a cleanup and isolates the code from future changes to Reloc::Model. llvm-svn: 269909
* [mips][ias] EF_MIPS_MICROMIPS should iff microMIPS code was emitted.Daniel Sanders2016-05-161-0/+7
| | | | | | | | | | | | | | | Summary: This fixes PR27682. Additionally, '.set micromips' by itself is not sufficient to raise the EF_MIPS_MICROMIPS flag. It is also necessary to emit a microMIPS instruction. This has also been fixed. Reviewers: sdardis, vkalintiris, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20214 llvm-svn: 269639
* [mips] Addition of a third operand to the instructions [d]div, [d]divuZoran Jovanovic2016-05-161-9/+8
| | | | | | | | | Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
* [mips][ias] Fix O32 .cprestore directive when inside .set noat region and ↵Daniel Sanders2016-05-121-11/+8
| | | | | | | | | | | | | | | | | | offset is in range. Summary: This expands on r269179 to fix an additional case that was not covered by our tests. The assembler temporary is not needed when the .cprestore offset fits inside a simm16 and it is not an error to use it inside a '.set noat' in this case. Reviewers: emaste, seanbruno, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20199 llvm-svn: 269295
* [mips][ias] Fix N32 and N64 .cprestore directive when inside .set noat region.Daniel Sanders2016-05-111-4/+2
| | | | | | | | | | | | | | | | | | Summary: r268058 unintentionally made the retrieval of the current assembler temporary unconditional. This was fine for the existing tests but it broke the cases where the assembler temporary is not needed (N32/N64 or not PIC) and is unavailable due to a '.set noat' directive. This fixes FreeBSD's libc. Reviewers: emaste, sdardis, seanbruno Subscribers: dsanders, emaste, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20093 llvm-svn: 269179
* [mips] Fix a partially initialized member variable that was introduced in ↵Daniel Sanders2016-05-091-0/+2
| | | | | | r268896. llvm-svn: 268938
* [mips][micromips] Make getPointerRegClass() result depend on the instruction.Daniel Sanders2016-05-091-0/+5
| | | | | | | | | | | | | | | | | | | Summary: Previously, it returned the GPR16MMRegClass for all instructions which was incorrect for instructions like lwsp/lwgp and unnecesarily restricted the permitted registers for instructions like lw32. This fixes quite a few of the -verify-machineinstrs errors reported in PR27458. I've only added -verify-machineinstrs to one test in this change since I understand there is a plan to enable the verifier by default. Reviewers: hvarga, zbuljan, zoran.jovanovic, sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19873 llvm-svn: 268918
* [mips] Fix use after free and an unnecessary copy introduced in r268896.Daniel Sanders2016-05-091-3/+4
| | | | llvm-svn: 268913
* Revert "[Mips] Fix use after free."Benjamin Kramer2016-05-091-1/+2
| | | | | | | | Fixes use after free but breaks tests. This reverts commit r268901. llvm-svn: 268902
* [Mips] Fix use after free.Benjamin Kramer2016-05-091-2/+1
| | | | llvm-svn: 268901
* [mips][microMIPS] Implement LWP and SWP instructionsZlatko Buljan2016-05-091-7/+26
| | | | | | Differential Revision: http://reviews.llvm.org/D10640 llvm-svn: 268896
* Fix Mips Parser error reportingNirav Dave2016-05-051-27/+49
| | | | | | | | | | | | | [mips] On error, ParseDirective should always return false to signify that the directive was understood. Reviewers: dsanders, vkalintiris, sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19929 llvm-svn: 268630
* [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add ↵Zlatko Buljan2016-05-041-1/+9
| | | | | | | | tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions Differential Revision: http://reviews.llvm.org/D19857 llvm-svn: 268491
* [mips] Use MipsMCExpr instead of MCSymbolRefExpr for all relocations.Daniel Sanders2016-05-031-119/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is much closer to the way MIPS relocation expressions work (%hi(foo + 2) rather than %hi(foo) + 2) and removes the need for the various bodges in MipsAsmParser::evaluateRelocExpr(). Removing those bodges ensures that the constant stored in MCValue is the full 32 or 64-bit (depending on ABI) offset from the symbol. This will be used to correct the %hi/%lo matching needed to sort the relocation table correctly. As part of this: * Gave MCExpr::print() the ability to omit parenthesis when emitting a symbol reference inside a MipsMCExpr operator like %hi(X). Without this we print things like %lo(($L1)). * %hi(%neg(%gprel(X))) is now three MipsMCExpr's instead of one. Most of the related special cases have been removed or moved to MipsMCExpr. We can remove the rest as we gain support for the less common relocations when they are not part of this specific combination. * Renamed MipsMCExpr::VariantKind and the enum prefix ('VK_') to avoid confusion with MCSymbolRefExpr::VariantKind and its prefix (also 'VK_'). * fixup_Mips_GOT_Local and fixup_Mips_GOT_Global were found to be identical and merged into fixup_Mips_GOT. * MO_GOT16 and MO_GOT turned out to be identical and have been merged into MO_GOT. * VK_Mips_GOT and VK_Mips_GOT16 turned out to be the same thing so they have been merged into MEK_GOT Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19716 llvm-svn: 268379
* [mips][ias] Move createCpRestoreMemOp to MipsTargetStreamer. NFC.Daniel Sanders2016-04-291-19/+14
| | | | | | | | | | | | | | | Summary: This removes the temporary call to isIntegratedAssemblerRequired() which was added recently. It's effect is now acheived directly in the MipsTargetStreamer hierarchy. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19715 llvm-svn: 268058
* [mips][ias] Split expandMemInst between MipsAsmParser and ↵Daniel Sanders2016-04-291-66/+91
| | | | | | | | | | | | | | | | | | | | | | MipsTargetStreamer. Almost NFC. Summary: The portion in MipsAsmParser is responsible for figuring out which expansion to use, while the portion in MipsTargetStreamer is responsible for emitting it. This allows us to remove the call to isIntegratedAssemblerRequired() which is currently ensuring the effect of .cprestore only occurs when writing objects. The small functional change is that the memory offsets are now correctly printed as signed values. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19714 llvm-svn: 268042
* [mips][ias] Moved most instruction emission helpers to MipsTargetStreamer. NFC.Daniel Sanders2016-04-291-279/+208
| | | | | | | | | | | | | | | | | | | Summary: * Moved all the emit*() helpers to MipsTargetStreamer. * Moved createNop() to MipsTargetStreamer as emitNop() and emitEmptyDelaySlot(). This instruction has been split to distinguish between the 'nop' instruction and the nop used in delay slots which is sometimes a different nop to the 'nop' instruction (e.g. for short delay slots on microMIPS). * Moved createAddu() to MipsTargetStreamer as emitAddu(). * Moved createAppropriateDSLL() to MipsTargetStreamer as emitDSLL(). Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19712 llvm-svn: 268041
* [mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructionsZlatko Buljan2016-04-291-7/+0
| | | | | | Differential Revision: http://reviews.llvm.org/D18645 llvm-svn: 268012
* [mips][microMIPS] Revert commit r266977Zlatko Buljan2016-04-251-9/+1
| | | | | | Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ... llvm-svn: 267418
* [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructionsZlatko Buljan2016-04-221-1/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D18687 llvm-svn: 267114
* [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL ↵Zlatko Buljan2016-04-211-1/+9
| | | | | | | | instructions and add tests for LWM32 and SWM32 Differential Revision: http://reviews.llvm.org/D19150 llvm-svn: 266977
* MipsAsmParser::loadImmediate(): Prune an obsolete \param in r266602. ↵NAKAMURA Takumi2016-04-201-1/+0
| | | | | | [-Wdocumentation] llvm-svn: 266841
* [mips][ias] Prevent double-filling of delay slots by generating '.set ↵Daniel Sanders2016-04-181-1/+8
| | | | | | | | | | | | | | | | | | noreorder' regions. Summary: When clang is given -save-temps or -via-file-asm, any inline assembly in the source is parsed twice. Once by the compiler, and again by the assembler. We must take care to ensure that this doesn't lead to double-filling delay slots. Reviewers: sdardis, vkalintiris Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19166 llvm-svn: 266608
* [mips][ias] Stream macro expansions to output instead of buffering them. NFC.Daniel Sanders2016-04-181-337/+326
| | | | | | | | | | | | | | | | | | | Summary: This will allows us to eliminate some magic numbers from the offset operand of branch instructions in favour of symbols and makes it possible to avoid double-filling delay slots when clang is given -save-temps. parseDirectiveCpRestore() is calling isIntegratedAssemblerRequired() for the moment since correctly pushing the generation of these instructions into the ELF target streamer is tricky enough to warrant a separate patch. Reviewers: sdardis, vkalintiris Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19164 llvm-svn: 266602
* [NFC] Header cleanupMehdi Amini2016-04-181-1/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [mips] add assembler support for .set arch=octeonPetar Jovanovic2016-04-121-1/+1
| | | | | | | | | | | This patch enables assembler support for .set arch=octeon. It will fix issues with inline assembler when this directive is used. Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D18548 llvm-svn: 266081
* [mips] Range check simm32 and fold MIPS16's imm32 into simm32.Daniel Sanders2016-04-041-0/+4
| | | | | | | | | | | | | | Summary: At this point we should be able to enable IAS by default for O32 without breaking check-all, or recursion. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18439 llvm-svn: 265302
* [mips] Range check simm16Daniel Sanders2016-03-311-0/+19
| | | | | | | | | | | | | | | | | | | Summary: There are too many instructions to exhaustively test so addiu and lwc2 are used as representative examples. It should be noted that many memory instructions that should have simm16 range checking do not because it is also necessary to support the macro of the same name which accepts simm32. The range checks for these occur in the macro expansion. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18437 llvm-svn: 265019
* [mips] Range check simm11 and mem_simm11.Daniel Sanders2016-03-311-0/+6
| | | | | | | | | | | | | | | | | | Summary: ldc2/sdc2 now emit slightly worse diagnostics for MIPS-I. The problem is that they don't trigger the custom parser because all the candidates are disabled by feature bits. On all other subtargets, the diagnostics are accurate but are subject to the usual issues of needing to report multiple ways to correct the code (e.g. smaller offset, enable a CPU feature) but only being able to report one error. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18436 llvm-svn: 265018
* [mips] Split mem_msa into range checked mem_simm10 and mem_simm10_lsl[123]Daniel Sanders2016-03-311-3/+17
| | | | | | | | | | | | | | Summary: Also, made test_mi10.s formatting consistent with the majority of the MC tests. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18435 llvm-svn: 265014
* [mips] Range check simm9 and fix a bug this revealed.Daniel Sanders2016-03-311-0/+6
| | | | | | | | | | | | | | Summary: The bug was that microMIPS's [ls]w[lr]e instructions claimed to support a 12-bit offset when it is only 9-bit. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18434 llvm-svn: 265010
* [mips] Correct MIPS16 jal/jalx to have uimm26 offsets and add MC layer range ↵Daniel Sanders2016-03-291-0/+3
| | | | | | | | | | | | | | | | checks. NFC. Summary: However, this has no effect at this time because the instructions affected are marked 'isCodeGenOnly=1' and have no alternative for the MC layer. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18179 llvm-svn: 264712
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