summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
Commit message (Expand)AuthorAgeFilesLines
* [Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trapKrzysztof Parzyszek2019-02-211-0/+32
* Revert r354606, it breaks asan testsKrzysztof Parzyszek2019-02-211-32/+0
* [Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trapKrzysztof Parzyszek2019-02-211-0/+32
* [Hexagon] Remove incorrect bit negationKrzysztof Parzyszek2019-01-231-1/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [Hexagon] Fix post-ra expansion of PS_wselectKrzysztof Parzyszek2018-12-071-1/+0
* Fix gcc7.3 -Wparentheses warning. NFCI.Simon Pilgrim2018-12-071-3/+3
* [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operandFrancis Visoiu Mistrih2018-11-281-16/+18
* Remove FrameAccess struct from hasLoadFromStackSlotSander de Smalen2018-09-051-2/+2
* Extend hasStoreToStackSlot with list of FI accesses.Sander de Smalen2018-09-031-10/+10
* [Hexagon] Expand vgather pseudos during packetizationKrzysztof Parzyszek2018-08-171-75/+87
* [MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth2018-08-161-11/+10
* [Hexagon] Remove 'T' from HasVNN predicates, NFCKrzysztof Parzyszek2018-06-201-3/+3
* [Hexagon] Late predicate producers cannot be used as dot-new sourcesKrzysztof Parzyszek2018-06-111-4/+23
* [Hexagon] Implement vector-pair zero as V6_vsubw_dvKrzysztof Parzyszek2018-06-061-0/+8
* [Hexagon] Generate post-increment for floating point typesBrendon Cahoon2018-05-181-0/+2
* [Hexagon] Add a target feature for generating new-value storesKrzysztof Parzyszek2018-05-141-0/+3
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-20/+22
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-091-6/+6
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-3/+3
* [Hexagon] Remove default values from lambda parametersKrzysztof Parzyszek2018-04-051-23/+23
* [Hexagon] Add support for "new" circular buffer intrinsicsKrzysztof Parzyszek2018-03-281-76/+134
* [Pipeliner] Use latency to compute RecMIIKrzysztof Parzyszek2018-03-261-3/+3
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-231-1/+1
* [Hexagon] Make findLoopInstr member of HexagonInstrInfoKrzysztof Parzyszek2018-03-231-3/+7
* [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned onesKrzysztof Parzyszek2018-03-071-0/+5
* [Hexagon] Add code to select QTRUE and QFALSEKrzysztof Parzyszek2018-02-091-0/+14
* [Hexagon] Implement hasLoadFromStackSlot and hasStoreToStackSlotKrzysztof Parzyszek2018-01-231-0/+36
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-111-15/+167
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-4/+4
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-9/+9
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-4/+4
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-281-2/+2
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-3/+3
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* [Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek2017-10-201-1/+5
* [Hexagon] Mark vector loads as predicable, update instruction mappingsKrzysztof Parzyszek2017-10-181-0/+25
* [Hexagon] Handle non-immediate operands to A2_addi in getIncrementValueKrzysztof Parzyszek2017-10-111-4/+6
* [Pipeliner] Fix offset value for instrs dependent on post-inc load/storesKrzysztof Parzyszek2017-10-111-7/+8
* [Pipeliner] Improve serialization order for post-incrementsKrzysztof Parzyszek2017-10-111-1/+6
* [Hexagon] Give uniform names to functions changing addressing modes, NFCKrzysztof Parzyszek2017-10-051-26/+29
* [Hexagon] Add a member Subtarget to HexagonInstrInfo, NFCKrzysztof Parzyszek2017-10-041-51/+24
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ot...Eugene Zelenko2017-09-281-85/+90
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-248/+125
* [Hexagon] Make getMemAccessSize return size in bytesKrzysztof Parzyszek2017-09-141-13/+18
* [Hexagon] Fix a bug in r308502: post-inc offset is always 0Krzysztof Parzyszek2017-07-191-2/+2
* [Hexagon] Handle subregisters in areMemAccessesTriviallyDisjointKrzysztof Parzyszek2017-07-191-15/+32
* [Hexagon] Handle subregisters and non-immediates in getBaseAndOffsetKrzysztof Parzyszek2017-07-191-6/+14
* [Hexagon] Add support for nontemporal loads and stores on HVXKrzysztof Parzyszek2017-07-111-1/+29
* [Hexagon] Fix check for HMOTF_ConstExtend operand flagKrzysztof Parzyszek2017-07-101-8/+3
OpenPOWER on IntegriCloud