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author | Sander de Smalen <sander.desmalen@arm.com> | 2018-09-05 08:59:50 +0000 |
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committer | Sander de Smalen <sander.desmalen@arm.com> | 2018-09-05 08:59:50 +0000 |
commit | c91b27d9ee6e3bc49525532680dd636f1d5a1eed (patch) | |
tree | 0e4b8c03217e0279369c309f26d80cd468b82c17 /llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | |
parent | 445bdd171ff4268157256923a1f143ec959d9366 (diff) | |
download | bcm5719-llvm-c91b27d9ee6e3bc49525532680dd636f1d5a1eed.tar.gz bcm5719-llvm-c91b27d9ee6e3bc49525532680dd636f1d5a1eed.zip |
Remove FrameAccess struct from hasLoadFromStackSlot
This removes the FrameAccess struct that was added to the interface
in D51537, since the PseudoValue from the MachineMemoryOperand
can be safely casted to a FixedStackPseudoSourceValue.
Reviewers: MatzeB, thegameg, javed.absar
Reviewed By: thegameg
Differential Revision: https://reviews.llvm.org/D51617
llvm-svn: 341454
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp')
-rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 20ed6a995f2..a3c160d01f8 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -337,7 +337,7 @@ unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI, /// operand of that instruction if true. bool HexagonInstrInfo::hasLoadFromStackSlot( const MachineInstr &MI, - SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const { + SmallVectorImpl<const MachineMemOperand *> &Accesses) const { if (MI.isBundle()) { const MachineBasicBlock *MBB = MI.getParent(); MachineBasicBlock::const_instr_iterator MII = MI.getIterator(); @@ -355,7 +355,7 @@ bool HexagonInstrInfo::hasLoadFromStackSlot( /// operand of that instruction if true. bool HexagonInstrInfo::hasStoreToStackSlot( const MachineInstr &MI, - SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const { + SmallVectorImpl<const MachineMemOperand *> &Accesses) const { if (MI.isBundle()) { const MachineBasicBlock *MBB = MI.getParent(); MachineBasicBlock::const_instr_iterator MII = MI.getIterator(); |