| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [Hexagon] Remove the remnants of isConstExtProfitable | Krzysztof Parzyszek | 2015-10-20 | 1 | -1/+0 |
| * | [Hexagon] Adding skeleton of HVX extension instructions. | Colin LeMahieu | 2015-10-17 | 1 | -0/+45 |
| * | [Hexagon] Disassembling, printing, and emitting instructions a whole-bundle a... | Colin LeMahieu | 2015-05-29 | 1 | -2/+0 |
| * | [Hexagon] Separating InstHexagon from OpcodeHexagon. | Colin LeMahieu | 2015-03-10 | 1 | -28/+35 |
| * | [Hexagon] Removing v2-4 flags. V4 is the minimum supported version. | Colin LeMahieu | 2015-02-09 | 1 | -20/+11 |
| * | [Hexagon] Since decoding conflicts have been resolved, isCodeGenOnly = 0 by d... | Colin LeMahieu | 2015-02-05 | 1 | -1/+0 |
| * | [Hexagon] Revert change to isCodeGenOnly = 1 in r228080 | Colin LeMahieu | 2015-02-04 | 1 | -0/+1 |
| * | [Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them t... | Colin LeMahieu | 2015-02-04 | 1 | -1/+0 |
| * | [Hexagon] Reapplying 224775 load words. | Colin LeMahieu | 2014-12-23 | 1 | -0/+1 |
| * | [Hexagon] Adding encodings for JR class instructions. Updating complier usages. | Colin LeMahieu | 2014-12-10 | 1 | -1/+1 |
| * | [Hexagon] Adding basic disassembler. | Colin LeMahieu | 2014-10-22 | 1 | -6/+13 |
| * | [Hexagon] Add new InstrItinClass to support timing classes. | Jyotsna Verma | 2014-05-08 | 1 | -52/+53 |
| * | [Hexagon] Add New TSFlags to be used in the upcoming patches. | Jyotsna Verma | 2014-05-07 | 1 | -22/+40 |
| * | Even more spelling fixes for "instruction". | Robert Wilhelm | 2013-09-28 | 1 | -1/+1 |
| * | Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. | Jyotsna Verma | 2013-05-10 | 1 | -0/+2 |
| * | Hexagon: Set accessSize and addrMode on all load/store instructions. | Jyotsna Verma | 2013-05-07 | 1 | -0/+1 |
| * | Hexagon: Change insn class to support instruction encoding. | Jyotsna Verma | 2013-02-14 | 1 | -219/+193 |
| * | Added multiclass for post-increment load instructions. | Jyotsna Verma | 2012-11-14 | 1 | -3/+62 |
| * | Use the relationship models infrastructure to add two relations - getPredOpcode | Pranav Bhandarkar | 2012-11-01 | 1 | -0/+10 |
| * | Hexagon V5 FP Support. | Sirish Pande | 2012-05-10 | 1 | -2/+2 |
| * | Extensions of Hexagon V4 instructions. | Sirish Pande | 2012-05-03 | 1 | -28/+108 |
| * | Revert r155365, r155366, and r155367. All three of these have regression | Chandler Carruth | 2012-04-23 | 1 | -99/+22 |
| * | Hexagon V5 (floating point) support. | Sirish Pande | 2012-04-23 | 1 | -2/+2 |
| * | Support for Hexagon VLIW Packetizer. | Sirish Pande | 2012-04-23 | 1 | -22/+99 |
| * | This reverts a long string of commits to the Hexagon backend. These | Chandler Carruth | 2012-04-18 | 1 | -74/+22 |
| * | Hexagon V5 (Floating Point) Support. | Sirish Pande | 2012-04-16 | 1 | -2/+2 |
| * | HexagonPacketizer patch. | Sirish Pande | 2012-04-12 | 1 | -22/+74 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -8/+8 |
| * | Use TSFlag bit to describe instruction properties. | Brendon Cahoon | 2012-02-08 | 1 | -6/+20 |
| * | Hexagon backend support | Tony Linthicum | 2011-12-12 | 1 | -0/+242 |
