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path: root/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [Hexagon] Change instruction type field in TSFlags to 7 bitsKrzysztof Parzyszek2018-12-031-36/+36
* [Hexagon] Remove support for V4Krzysztof Parzyszek2018-10-191-15/+1
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-111-14/+20
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-2/+1
* [Hexagon] Make getMemAccessSize return size in bytesKrzysztof Parzyszek2017-09-141-8/+9
* [Hexagon] Use automatically-generated scheduling information for HVXKrzysztof Parzyszek2017-05-031-160/+4
* [Hexagon] Remove unused validSubtarget TSFlagsKrzysztof Parzyszek2017-05-021-16/+0
* [Hexagon] Replace CVI_VM_CUR_LD type with CVI_VM_LDKrzysztof Parzyszek2017-05-011-0/+3
* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-101-75/+17
* [Hexagon] Update instruction typesKrzysztof Parzyszek2017-02-071-14/+38
* [Hexagon] Update MCTargetDescKrzysztof Parzyszek2017-02-061-31/+32
* Fix spelling mistakes in Hexagon target comments. NFC.Simon Pilgrim2016-11-171-1/+1
* [Hexagon] Adding change of flow max 1 (cofMax1) TS flag for marking this rest...Colin LeMahieu2016-10-081-0/+3
* [Hexagon] Update instruction itinerariesKrzysztof Parzyszek2016-07-151-10/+4
* [Hexagon] Remove the remnants of isConstExtProfitableKrzysztof Parzyszek2015-10-201-1/+0
* [Hexagon] Adding skeleton of HVX extension instructions.Colin LeMahieu2015-10-171-0/+45
* [Hexagon] Disassembling, printing, and emitting instructions a whole-bundle a...Colin LeMahieu2015-05-291-2/+0
* [Hexagon] Separating InstHexagon from OpcodeHexagon.Colin LeMahieu2015-03-101-28/+35
* [Hexagon] Removing v2-4 flags. V4 is the minimum supported version.Colin LeMahieu2015-02-091-20/+11
* [Hexagon] Since decoding conflicts have been resolved, isCodeGenOnly = 0 by d...Colin LeMahieu2015-02-051-1/+0
* [Hexagon] Revert change to isCodeGenOnly = 1 in r228080Colin LeMahieu2015-02-041-0/+1
* [Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them t...Colin LeMahieu2015-02-041-1/+0
* [Hexagon] Reapplying 224775 load words.Colin LeMahieu2014-12-231-0/+1
* [Hexagon] Adding encodings for JR class instructions. Updating complier usages.Colin LeMahieu2014-12-101-1/+1
* [Hexagon] Adding basic disassembler.Colin LeMahieu2014-10-221-6/+13
* [Hexagon] Add new InstrItinClass to support timing classes.Jyotsna Verma2014-05-081-52/+53
* [Hexagon] Add New TSFlags to be used in the upcoming patches.Jyotsna Verma2014-05-071-22/+40
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-281-1/+1
* Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.Jyotsna Verma2013-05-101-0/+2
* Hexagon: Set accessSize and addrMode on all load/store instructions.Jyotsna Verma2013-05-071-0/+1
* Hexagon: Change insn class to support instruction encoding.Jyotsna Verma2013-02-141-219/+193
* Added multiclass for post-increment load instructions.Jyotsna Verma2012-11-141-3/+62
* Use the relationship models infrastructure to add two relations - getPredOpcodePranav Bhandarkar2012-11-011-0/+10
* Hexagon V5 FP Support.Sirish Pande2012-05-101-2/+2
* Extensions of Hexagon V4 instructions.Sirish Pande2012-05-031-28/+108
* Revert r155365, r155366, and r155367. All three of these have regressionChandler Carruth2012-04-231-99/+22
* Hexagon V5 (floating point) support.Sirish Pande2012-04-231-2/+2
* Support for Hexagon VLIW Packetizer.Sirish Pande2012-04-231-22/+99
* This reverts a long string of commits to the Hexagon backend. TheseChandler Carruth2012-04-181-74/+22
* Hexagon V5 (Floating Point) Support.Sirish Pande2012-04-161-2/+2
* HexagonPacketizer patch.Sirish Pande2012-04-121-22/+74
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-8/+8
* Use TSFlag bit to describe instruction properties.Brendon Cahoon2012-02-081-6/+20
* Hexagon backend supportTony Linthicum2011-12-121-0/+242
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