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path: root/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
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* Hexagon: Use multiclass for Jump instructions.Jyotsna Verma2013-05-011-2/+30
* Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.Tim Northover2013-04-201-10/+0
* Hexagon: Expand br_cc.Jyotsna Verma2013-04-041-0/+2
* DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard2013-03-081-1/+3
* Hexagon: Handle i8, i16 and i1 Var Args.Jyotsna Verma2013-03-071-0/+10
* Hexagon: Add support to lower block address.Jyotsna Verma2013-03-071-0/+12
* reverting patch 176508.Jyotsna Verma2013-03-051-12/+0
* Hexagon: Add support for lowering block address.Jyotsna Verma2013-03-051-0/+12
* Hexagon: Expand addc, adde, subc and sube.Jyotsna Verma2013-03-051-0/+23
* Hexagon: Expand cttz, ctlz, and ctpop for now.Anshuman Dasgupta2013-02-211-0/+5
* Update TargetLowering ivars for name policy.Jim Grosbach2013-02-201-2/+2
* Move MRI liveouts to Hexagon return instructions.Jakob Stoklund Olesen2013-02-051-10/+9
* Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng2013-01-291-0/+2
* Improve r172468: const_cast is not needed hereDmitri Gribenko2013-01-141-3/+2
* Fix Another CastDavid Greene2013-01-141-1/+2
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-7/+7
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-8/+8
* Finish the renaming.Rafael Espindola2012-11-211-1/+1
* TargetLowering interface to set/get minimum block entries for jump tables.Sebastian Pop2012-09-251-0/+2
* Remove tabs.Bill Wendling2012-07-191-4/+4
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-021-2/+2
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-251-7/+11
* Hexagon V5 FP Support.Sirish Pande2012-05-101-118/+246
* Revert r155365, r155366, and r155367. All three of these have regressionChandler Carruth2012-04-231-246/+118
* Hexagon V5 (floating point) support.Sirish Pande2012-04-231-118/+246
* llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build o...NAKAMURA Takumi2012-04-211-0/+1
* HexagonISelLowering.cpp: Reorder #includes.NAKAMURA Takumi2012-04-211-1/+2
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change s...Craig Topper2012-04-201-7/+7
* This reverts a long string of commits to the Hexagon backend. TheseChandler Carruth2012-04-181-248/+119
* Remove unused variableDavid Blaikie2012-04-161-1/+0
* Hexagon V5 (Floating Point) Support.Sirish Pande2012-04-161-119/+249
* Reorder includes in Target backends to following coding standards. Remove som...Craig Topper2012-03-171-3/+2
* Convert more static tables of registers used by calling convention to uint16_...Craig Topper2012-03-111-3/+3
* Re-commit r151623 with fix. Only issue special no-return calls if it's a dire...Evan Cheng2012-02-281-1/+1
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack pre...Daniel Dunbar2012-02-281-1/+1
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-281-1/+1
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-8/+6
* VLIW specific scheduler framework that utilizes deterministic finite automato...Andrew Trick2012-02-011-0/+1
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-2/+0
* Initializing to false makes better sense. Thanks, David.Chad Rosier2012-01-061-1/+1
* Fix uninitialized variable warning.Chad Rosier2012-01-061-1/+1
* Hexagon: Remove unused variables.Benjamin Kramer2011-12-181-5/+0
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-131-0/+2
* Hexagon backend supportTony Linthicum2011-12-121-0/+1503
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