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path: root/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
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* CodeGen: Use LLT instead of EVT in getRegisterByNameMatt Arsenault2020-01-091-1/+1
* Move tail call disabling code to target independent codeReid Kleckner2020-01-031-10/+1
* [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG fo...QingShan Zhang2020-01-031-0/+4
* [IR] Split out target specific intrinsic enums into separate headersReid Kleckner2019-12-111-1/+2
* DAG: Add function context to isFMAFasterThanFMulAndFAddMatt Arsenault2019-11-191-1/+2
* [SVE][CodeGen] Scalable vector MVT size queriesGraham Hunter2019-11-181-1/+1
* [Hexagon] Handle remaining registers in getRegisterByName()Krzysztof Parzyszek2019-10-291-2/+64
* TLI: Remove DAG argument from getRegisterByNameMatt Arsenault2019-10-011-4/+4
* [Alignment][NFC] Remove unneeded llvm:: scoping on Align typesGuillaume Chatelet2019-09-271-3/+3
* [TargetLowering] Make allowsMemoryAccess methode virtual.Thomas Raoux2019-09-261-2/+4
* [MVT] Add v256i1 to MachineValueTypeKrzysztof Parzyszek2019-09-201-7/+14
* [SVE][MVT] Fixed-length vector MVT rangesGraham Hunter2019-09-171-3/+3
* [Alignment][NFC] Use Align with TargetLowering::setPrefFunctionAlignmentGuillaume Chatelet2019-09-061-1/+1
* [Alignment][NFC] Use Align with TargetLowering::setPrefLoopAlignmentGuillaume Chatelet2019-09-061-1/+1
* [Alignment][NFC] Use Align with TargetLowering::setMinFunctionAlignmentGuillaume Chatelet2019-09-061-1/+1
* [Hexagon] Fix type in HexagonTargetLowering::ReplaceNodeResultsKrzysztof Parzyszek2019-09-051-1/+2
* [LLVM][Alignment] Make functions using log of alignment explicitGuillaume Chatelet2019-09-051-3/+3
* [Hexagon] Generate min/max instructions for 64-bit vectorsKrzysztof Parzyszek2019-08-161-3/+58
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-2/+2
* [Hexagon] Fix instruction selection for vselect v4i8Krzysztof Parzyszek2019-08-151-8/+14
* [Hexagon] Generate vector min/max for HVXKrzysztof Parzyszek2019-08-151-0/+11
* [LLVM][Alignment] Introduce Alignment TypeGuillaume Chatelet2019-08-051-2/+4
* [Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 foldRoman Lebedev2019-07-241-0/+4
* [Hexagon] Custom-lower UADDO(x, 1) and USUBO(x, 1)Krzysztof Parzyszek2019-07-011-2/+41
* [Hexagon] Change limit type to match the argument type (NFC)Evandro Menezes2019-06-191-1/+1
* [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR...Simon Pilgrim2019-06-121-2/+3
* [TargetLowering] Add allowsMemoryAccess(MachineMemOperand) helper wrapper. NFCI.Simon Pilgrim2019-06-111-5/+4
* [TargetLowering] Change getOptimalMemOpType to take a function attribute listSjoerd Meijer2019-04-301-1/+1
* [TargetLowering] Add code size information on isFPImmLegal. NFCAdhemerval Zanella2019-03-181-1/+2
* Implementation of asm-goto support in LLVMCraig Topper2019-02-081-2/+4
* [opaque pointer types] Pass function types to CallInst creation.James Y Knight2019-02-011-2/+2
* Reapply "IR: Add fp operations to atomicrmw"Matt Arsenault2019-01-221-2/+17
* Revert r351778: IR: Add fp operations to atomicrmwChandler Carruth2019-01-221-17/+2
* IR: Add fp operations to atomicrmwMatt Arsenault2019-01-221-2/+17
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [opaque pointer types] Remove some calls to generic Type subtype accessors.James Y Knight2019-01-101-5/+2
* [Hexagon] Add patterns for funnel shiftsKrzysztof Parzyszek2018-12-201-2/+9
* [Hexagon] Add instruction definitions for Hexagon V66Krzysztof Parzyszek2018-12-051-7/+11
* [x86] allow vector load narrowing with multi-use valuesSanjay Patel2018-11-101-0/+4
* [TargetLowering] Change TargetLoweringBase::getPreferredVectorAction to take ...Craig Topper2018-11-051-2/+2
* [Hexagon] Do not reduce load size for globals in small-dataKrzysztof Parzyszek2018-11-021-0/+15
* [Hexagon] Remove support for V4Krzysztof Parzyszek2018-10-191-121/+30
* [Hexagon] Fix extracting subvectors of non-HVX vNi1Krzysztof Parzyszek2018-10-021-1/+2
* [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IRAlex Bradbury2018-09-191-3/+6
* Add support for getRegisterByName.Sid Manning2018-09-071-0/+13
* Revert [Hexagon] Add support for getRegisterByName.Sid Manning2018-09-031-46/+0
* [Hexagon] Add support for getRegisterByName.Sid Manning2018-08-311-0/+46
* [Hexagon] Map ISD::TRAP to J2_trap0(#0)Krzysztof Parzyszek2018-08-091-15/+15
* [Hexagon] Diagnose misaligned absolute loads and storesKrzysztof Parzyszek2018-08-081-21/+68
* [Hexagon] Properly scale bit index when extracting elements from vNi1Krzysztof Parzyszek2018-07-251-1/+3
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