summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
diff options
context:
space:
mode:
authorJames Y Knight <jyknight@google.com>2019-02-01 20:43:25 +0000
committerJames Y Knight <jyknight@google.com>2019-02-01 20:43:25 +0000
commit7976eb58382b25d0e17490b9d77fb06cb000c95b (patch)
tree286450abb61ef79d2e7356e0d0d80dbbce0a728a /llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
parentc456309f67a9ea44038fb5d8a96c90d9c6965b67 (diff)
downloadbcm5719-llvm-7976eb58382b25d0e17490b9d77fb06cb000c95b.tar.gz
bcm5719-llvm-7976eb58382b25d0e17490b9d77fb06cb000c95b.zip
[opaque pointer types] Pass function types to CallInst creation.
This cleans up all CallInst creation in LLVM to explicitly pass a function type rather than deriving it from the pointer's element-type. Differential Revision: https://reviews.llvm.org/D57170 llvm-svn: 352909
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonISelLowering.cpp')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index b3781fe9e71..0b9f424822c 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -3116,12 +3116,12 @@ Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
: Intrinsic::hexagon_L4_loadd_locked;
+ Function *Fn = Intrinsic::getDeclaration(M, IntID);
PointerType *NewPtrTy
= Builder.getIntNTy(SZ)->getPointerTo(PT->getAddressSpace());
Addr = Builder.CreateBitCast(Addr, NewPtrTy);
- Value *Fn = Intrinsic::getDeclaration(M, IntID);
Value *Call = Builder.CreateCall(Fn, Addr, "larx");
return Builder.CreateBitCast(Call, Ty);
@@ -3140,7 +3140,7 @@ Value *HexagonTargetLowering::emitStoreConditional(IRBuilder<> &Builder,
assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
: Intrinsic::hexagon_S4_stored_locked;
- Value *Fn = Intrinsic::getDeclaration(M, IntID);
+ Function *Fn = Intrinsic::getDeclaration(M, IntID);
unsigned AS = Addr->getType()->getPointerAddressSpace();
Addr = Builder.CreateBitCast(Addr, CastTy->getPointerTo(AS));
OpenPOWER on IntegriCloud