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path: root/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
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* [Hexagon] Fixes to the bitsplit generationKrzysztof Parzyszek2017-03-091-11/+46
| | | | | | | | - Fix the insertion point, which occasionally could have been incorrect. - Avoid creating multiple bitsplits with the same operands, if an old one could be reused. llvm-svn: 297414
* [Hexagon] Use correct offset when extracting from the high wordKrzysztof Parzyszek2017-03-081-0/+1
| | | | | | | | When extracting a bitfield from the high register in a register pair, the final offset should be relative to the high register (for 32-bit extracts). llvm-svn: 297288
* [Hexagon] Check for presence before looking registers up in bit trackerKrzysztof Parzyszek2017-03-071-0/+4
| | | | llvm-svn: 297240
* [Hexagon] Generate bitsplit instructionKrzysztof Parzyszek2017-03-071-1/+118
| | | | llvm-svn: 297239
* [Hexagon] Do not insert instructions before PHI nodesKrzysztof Parzyszek2017-03-071-1/+3
| | | | llvm-svn: 297141
* [Hexagon] Generate extract instructions more aggressivelyKrzysztof Parzyszek2017-02-281-1/+201
| | | | llvm-svn: 296537
* Drop graph_ prefixDaniel Berlin2017-02-091-2/+2
| | | | llvm-svn: 294621
* GraphTraits: Add range versions of graph traits functions (graph_nodes, ↵Daniel Berlin2017-02-091-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | graph_children, inverse_graph_nodes, inverse_graph_children). Summary: Convert all obvious node_begin/node_end and child_begin/child_end pairs to range based for. Sending for review in case someone has a good idea how to make graph_children able to be inferred. It looks like it would require changing GraphTraits to be two argument or something. I presume inference does not happen because it would have to check every GraphTraits in the world to see if the noderef types matched. Note: This change was 3-staged with clang as well, which uses Dominators/etc from LLVM. Reviewers: chandlerc, tstellarAMD, dblaikie, rsmith Subscribers: arsenm, llvm-commits, nhaehnle Differential Revision: https://reviews.llvm.org/D29767 llvm-svn: 294620
* "Use" lambda captures which are otherwise only used in asserts. NFCDavid L. Jones2017-01-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: The LLVM coding standards recommend "using" values that are only needed by asserts: http://llvm.org/docs/CodingStandards.html#assert-liberally Without this change, LLVM cannot bootstrap with -Werror as the second stage fails with this new warning: https://reviews.llvm.org/rL291905 See also the previous fixes: https://reviews.llvm.org/rL291916 https://reviews.llvm.org/rL291939 https://reviews.llvm.org/rL291940 https://reviews.llvm.org/rL291941 Reviewers: rsmith Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28695 llvm-svn: 291957
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-131-1/+1
| | | | | | | | | | | Rename from addOperand to just add, to match the other method that has been added to MachineInstrBuilder for adding more than just 1 operand. See https://reviews.llvm.org/D28057 for the whole discussion. Differential Revision: https://reviews.llvm.org/D28556 llvm-svn: 291891
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2016-12-131-102/+87
| | | | | | other minor fixes (NFC). llvm-svn: 289604
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-091-44/+58
| | | | | | | | | | | For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
* [Hexagon] Avoid replacing full regs with subregisters in tied operandsKrzysztof Parzyszek2016-10-061-0/+20
| | | | | | Doing so will result in the two-address pass generating incorrect code. llvm-svn: 283463
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-1/+1
| | | | llvm-svn: 283004
* [Hexagon] Standardize next batch of pseudo instructionsKrzysztof Parzyszek2016-08-161-5/+5
| | | | | | | | | | | | | ALIGNA PS_aligna ALLOCA PS_alloca TFR_FI PS_fi TFR_FIA PS_fia TFR_PdFalse PS_false TFR_PdTrue PS_true VMULW PS_vmulw VMULW_ACC PS_vmulw_acc llvm-svn: 278832
* Use the range variant of find_if instead of unpacking begin/endDavid Majnemer2016-08-121-2/+2
| | | | | | No functionality change is intended. llvm-svn: 278443
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-1/+1
| | | | | | | | | If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278433
* [Hexagon] Use integer instructions for floating point immediatesKrzysztof Parzyszek2016-08-101-3/+3
| | | | | | | | | | | | Floating point instructions use general purpose registers, so the few instructions that can put floating point immediates into registers are, in fact, integer instruction. Use them explicitly instead of having pseudo-instructions specifically for dealing with floating point values. Simplify the constant loading instructions (from sdata) to have only two: one for 32-bit values and one for 64-bit values: CONST32 and CONST64. llvm-svn: 278244
* [Hexagon] Validate register class when doing bit simplificationKrzysztof Parzyszek2016-08-041-10/+33
| | | | llvm-svn: 277740
* [Hexagon] Generate COPY/REG_SEQUENCE more aggressively for vectorsKrzysztof Parzyszek2016-08-031-21/+27
| | | | llvm-svn: 277626
* [Hexagon] Recognize vcombine in copy propagationKrzysztof Parzyszek2016-08-021-2/+8
| | | | llvm-svn: 277528
* [HexagonBitSimplify] Remove dead code.Davide Italiano2016-07-301-18/+0
| | | | llvm-svn: 277284
* [Hexagon] Gracefully handle reg class mismatch in HexagonLoopRescheduleKrzysztof Parzyszek2016-07-261-13/+19
| | | | llvm-svn: 276793
* [Hexagon] Rerun bit tracker on new instructions in RIEKrzysztof Parzyszek2016-07-261-5/+7
| | | | | | | | | | | | | | | | | | | Consider this case: vreg1 = A2_zxth vreg0 (1) ... vreg2 = A2_zxth vreg1 (2) Redundant instruction elimination could delete the instruction (1) because the user (2) only cares about the low 16 bits. Then it could delete (2) because the input is already zero-extended. The problem is that the properties allowing each individual instruction to be deleted depend on the existence of the other instruction, so either one can be deleted, but not both. The existing check for this situation in RIE was insufficient. The fix is to update all dependent cells when an instruction is removed (replaced via COPY) in RIE. llvm-svn: 276792
* [Hexagon] Bitwise operations for insert/extract word not simplifiedKrzysztof Parzyszek2016-07-261-19/+70
| | | | | | | Change the bit simplifier to generate REG_SEQUENCE instructions in addition to COPY, which will handle cases of word insert/extract. llvm-svn: 276787
* Hexagon: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-121-5/+4
| | | | | | | | | | | | | | Avoid implicit iterator conversions from MachineInstrBundleIterator to MachineInstr* in the Hexagon backend, mostly by preferring MachineInstr& over MachineInstr* and switching to range-based for loops. There's a long tail of API cleanup here, but I'm planning to leave the rest to the Hexagon maintainers. HexagonInstrInfo defines many of its own predicates, and most of them still take MachineInstr*. Some of those actually check for nullptr, so I didn't feel comfortable changing them to MachineInstr& en masse. llvm-svn: 275142
* Delete more dead code.Rafael Espindola2016-06-211-13/+0
| | | | | | Found by gcc 6. llvm-svn: 273322
* Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.Benjamin Kramer2016-06-121-1/+1
| | | | | | No functionality change intended. llvm-svn: 272516
* Add optimization bisect opt-in calls for Hexagon passesAndrew Kaylor2016-04-261-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D19509 llvm-svn: 267593
* [NFC] Header cleanupMehdi Amini2016-04-181-5/+4
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfwordKrzysztof Parzyszek2016-01-141-3/+2
| | | | llvm-svn: 257815
* [Hexagon] Handle HVX registers in bit simplificationKrzysztof Parzyszek2016-01-141-0/+6
| | | | llvm-svn: 257811
* [Hexagon] Do not insert non-phis before phis in bit simplificationKrzysztof Parzyszek2016-01-131-7/+19
| | | | llvm-svn: 257606
* [Hexagon] Bit-based instruction simplificationKrzysztof Parzyszek2015-10-201-0/+2778
Analyze bit patterns of operands and values of instructions to perform various simplifications, dead/redundant code elimination, etc. llvm-svn: 250868
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